S-8243A Datasheet, PDF (12/34 Pages) Seiko Instruments Inc – BATTRY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Rev.2.4_00
„ Test Circuits
In this chapter test methods are explained for the case of S-8243B series, which is designed for 4-serial cell
pack. For the case of S-8243A series, which is designed for 3-serial cell, voltage source V2 should be
shorted, V3 should be read as V2, and V4 as V3.
1. Current consumption (Test circuit 1)
Current consumption at not monitoring V_BATOUT, I_OPE , is a current measured at the VSS pin when V1 = V2
= V3 = V4 = 3.5 V and V_MP = V_DD. Current consumption at power down, I_PDN, is a current measured at the
VSS pin when V1 = V2 = V3 = V4 = 1.5 V and V_MP = V_SS.
2. Voltage regulator (Test circuit 2)
Output voltage of the regulator V_OUT is a voltage measured at the VREG pin when V_DD = V_MP = 14 V and
I_OUT = 3 mA.
Line regulation of the voltage regulator ΔV_OUT1 is defined by the equation ΔV_OUT1 = V_OUT2−V_OUT1 where
V_OUT1 is the output voltage when V_DD = V_MP = 6 V and I_OUT = 3 mA, and V_OUT2 is the output voltage when
V_DD = V_MP = 18 V and I_OUT = 3 mA.
Load regulation of the regulator is defined by the equation ΔV_OUT2 = V_OUT3−V_OUT where V_OUT3 is the output
voltage when V_DD = V_MP = 14 V and I_OUT = 5 μA.
3. Battery monitor amp and pin current for VC1 to VC3 (Test circuit 3)
Voltage gain of the battery monitor amp for each cell is defined by the input offset voltage and the
measurement result provided from the VBATOUT pin for the combination of the CTL3 pin and CTL4 pin
expressed by the following table at the condition where V1 = V2 = V3 = V4 = 3.5 V. Pin current for VC1 to
VC3, I_VCn and I_VCnN are at the same time measured.
Table 8
CTL3 pin status
V_CTL3H min.
V_CTL3H min.
V_CTL3H min.
Open
Open
Open
V_CTL3L max.
V_CTL3L max.
CTL4 pin status
V_CTL4H min.
Open
V_CTL4L max.
V_CTL4H min.
Open
V_CTL4L max.
V_CTL4H min.
Open
VBATOUT pin output
V_OFF1
V_BAT1
V_OFF2
V_BAT2
V_OFF3
V_BAT3
V_OFF4
V_BAT4
VCn (n=1, 2, 3) pin current
I_VC1 at VC1 pin
⎯
I_VC2 at VC2 pin
⎯
I_VC3 at VC3 pin
⎯
I_VCnN at VCn pin (n=1, 2, 3)
⎯
Voltage gain of the battery monitor amp for each cell is calculated by the equation
GAMPn = (V_BATn −V_OFFn) / Vn (n = 1 to 4)
4. Overcharge detection voltages, overcharge detection hysteresis, overdischarge detection
voltages, overdischarge detection hysteresis, and overcurrent detection voltages (Test circuit 4)
〈〈Overcharge detection voltages, hysteresis voltages, and overdischarge detection voltages〉〉
In the following V_MP = V_DD and the CDT pin is open.
The COP pin and the DOP pin should provide “Low”, which is a voltage equal to V_DD × 0.1 V or lower,
in the condition that V1 = V2 = V3 = V4 = 3.5 V.
The overcharge detection voltage V_CU1 is defined by the voltage at which COP pin voltage becomes
“High”, which is a voltage equal to VDD × 0.9 V or higher, when the voltage V1 is gradually increased
from the starting condition V1 = 3.5 V. The overcharge release voltage V_CL1 is defined by the voltage
at which COP pin voltage becomes “Low” when the voltage V1 is gradually decreased. The
hysteresis voltage of the overcharge detection V_HC1 is then defined by the difference between the
overcharge detection voltage V_CU1 and the overcharge release voltage V_CL1.
12
Seiko Instruments Inc.