S-8243A Datasheet, PDF (13/34 Pages) Seiko Instruments Inc – BATTRY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

Rev.2.4_00
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
The overdischarge detection voltage V_DL1 is defined by the voltage at which DOP pin voltage
becomes “High” when the voltage V1 is gradually decreased from the starting condition V1 = 3.5 V.
The overdischarge release voltage V_DU1 is defined by the voltage at which DOP pin voltage becomes
“Low” when the voltage V1 is gradually increased. The hysteresis of the overdischarge detection
voltage V_HD1 is then defined by the difference between the overdischarge release voltage V_DU1 and
the overdischarge detection voltage V_DL1.
Other overcharge detection voltage V_CUn, hysteresis voltage of overcharge detection V_HCn,
overdischarge detection voltage V_DLn, and hysteresis of the overdischarge detection voltage V_HDn
( for n = 2 to 4) are defined in the same manner as in the case for n = 1.
〈〈Overcurrent detection voltages〉〉
Starting condition is V1 = V2 = V3 = V4 = 3.5 V, V_MP = V_DD, and the CDT pin is open. The DOP pin
voltage thus provides “Low”
The overcurrent detection voltage 1, V_IOV1 is defined by the voltage difference V_DD − V_MP at which the
DOP pin voltage becomes “High” when the voltage of VMP pin is decreased.
Starting condition for measuring the overcurrent detection voltage 2 and 3 is V1 = V2 = V3 = V4 = 3.5
V, V_MP = V_DD and the CDT pin voltage V_CDT = V_SS . The DOP pin voltage thus provides “Low”.
The overcurrent detection voltage 2, V_IOV2 is defined by the voltage difference V_DD−V_MP at which the
DOP pin voltage becomes “High” when the voltage of VMP pin is decreased.
The overcurrent detection delay time 2, t_IOV2 is a time needed for the DOP pin to become “High” from
“Low” when the VM pin voltage is changed quickly to V_IOV2 min.−0.2 V from the starting condition V_MP
= V_DD.
The overcurrent detection voltage 3, V_IOV3 is defined by the voltage of the VM pin at which the DOP
pin voltage becomes “High” when the voltage of VMP pin is decreased at the speed 10 V / ms.
The overcurrent detection delay time 3, t_IOV3 is a time needed for the DOP pin to become “High” from
“Low” when the VM pin voltage is changed quickly to V_IOV3 min.−0.2 V from the starting condition V_MP
= V_DD.
5. CTL1 pin current, overcharge detection delay, overdischarge detection delay, and overcurrent
detection delay 1 (Test circuit 5)
Starting condition is V1 = V2 = V3 = V4 = 3.5 V and V_MP = V_DD.
Current that flows between the CTL1 pin and V_SS is the CTL1 pin current I_CTL1L.
The overcharge detection delay time t_CU is a time needed for the COP pin voltage to change from “Low” to
“High” just after the V1 voltage is rapidly increased from 3.5 V to 4.5 V.
The overdischarge detection delay time t_DL is a time needed for the DOP pin voltage to change from
“Low” to “High” just after the V1 voltage is rapidly decreased from 3.5 V to 1.5 V.
The overcurrent detection delay time 1 is a time needed for the DOP pin voltage to change from “Low” to
“High” just after the VMP pin voltage is decreased from V_DD to V_DD−0.35 V when V1 = 3.5 V.
6. Input voltages for CTL1 and CTL2 (Test circuit 6)
Starting condition is V1 = V2 = V3 = V4 = 3.5 V.
Pin voltages of the COP and the DOP should be “High” when V_CTL1 = V_CTL1H min. and CTL2 is OPEN.
Pin voltages of the COP and the DOP should be “Low” when V_CTL1 = V_CTL1L max. and CTL2 is OPEN.
Pin voltage of the COP is “High” and the pin voltage of the DOP is “Low” when V_CTL1 = V_CTL1L max. and
V_CTL2 = V_CTL2H min.
Pin voltage of the COP is “Low” and the pin voltage of the DOP is “High” when V_CTL1 = V_CTL1L max. and
V_CTL2 = V_CTL2L max.
Seiko Instruments Inc.
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