S-8243A Datasheet, PDF (16/34 Pages) Seiko Instruments Inc – BATTRY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Rev.2.4_00
„ Operation
1. Battery protection circuit
Battery protection protects batteries from overcharge and overdischarge, and also protects external
FETs from overcurrent.
1-1 Normal condition
When all of the battery voltages are in the range from V_DLn to V_CUn and the discharge current is lower
than a specified value (the VMP pin voltage is lower than V_IOV1), the charging and discharging FETs
are turned on.
1-2 Overcharge condition
When any one of the battery voltages becomes higher than V_CUn and the state continues for t_CU or
longer, the COP pin becomes high impedance and is pulled up to EB+ pin voltage by an external
resistor, and the charging FET is turned off to stop charging. The overcharge condition is released
when one of the following two conditions holds.
a) All battery voltages become lower than V_CUn + V_HCn.
b) V_DD−V_MP>V_IOV1 (A load is connected, and discharging starts.)
1-3 Overdischarge condition
When any one of the battery voltages becomes lower than V_DLn and the state continues for t_DL or
longer, the DOP pin voltage becomes V_DD level, and the discharging FET is turned off to stop
discharging. After discharging is stopped due to overdischarge condition, the S-8243 enters power
down condition.
1-4 Power down condition
After stopping discharging due to overdischarge condition, the S-8243 enters power down condition.
In this condition, almost all circuits of the S-8243 are stopped to save current consumption. The
current consumption becomes lower than I_PDN. In the power down condition, the VMP pin is pulled
down to V_SS level by the internal R_VSM resistor. In power down condition, output pin voltages are fixed
at the following levels.
a) COP
b) DOP
c) VREG
V_SS (Charging FET is turned on)
V_DD (Discharging FET is turned off)
V_SS (Voltage regulator circuit is off)
d) VBATOUT V_SS (Battery voltage monitor amp circuit is off)
The power down condition is released when the following condition holds.
a) V_MP>V_IOV3 (A charger is connected, and charging starts.)
The overdischarging status is released when the following condition holds.
a) All of the battery voltages are V_DLn or higher, and the VMP pin voltage is V_DD/2 or higher. (A
charger is connected.)
1-5 Overcurrent condition
The S-8243 has three overcurrent detection levels (V_IOV1, V_IOV2 and V_IOV3) and three overcurrent
detection delay times (t_IOV1, t_IOV2 and t_IOV3) corresponding to each overcurrent detection levels. When
the discharging current becomes higher than a specified value (the voltage between V_DD and V_MP is
greater than V_IOV1) and the state continues for t_IOV1 or longer, the S-8243 enters the overcurrent
condition in which the DOP pin voltage becomes V_DD level to turn off the discharging FET to stop
discharging, the COP pin becomes high impedance and is pulled up to EB+ pin voltage by an
external resistor to turn off the charging FET to stop charging, and the VMP pin is pulled up to V_DD
voltage by the internal resistor R_VDM. Operation of two other overcurrent detection levels (V_IOV2 and
V_IOV3) and overcurrent detection delay times (t_IOV2 and t_IOV3) is the same as that for V_IOV1 and t_IOV1.
The overcurrent condition is released when the following condition holds.
a) V_MP>{V_IOV3 / (1−V_IOV3) × 3 / 5−2 / 5} × R_VDM
(A load is released, and the impedance between the EB− and EB+ pin becomes higher.)
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Seiko Instruments Inc.