C511_1 Datasheet, PDF (95/128 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Interrupt System
Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle
labeled C3 in figure 7-2 then, in accordance with the above rules, it will be vectored to during C5
and C6 without any instruction for the lower priority routine to be executed.
Thus, the processor acknowledges an interrupt request by executing a hardware-generated LCALL
to the appropriate servicing routine. In some cases it also clears the flag that generated the
interrupt, while in other cases it does not. Then this has to be done by the user’s software. The
hardware clears the external interrupt flags IE0 and IE1 only if they were transition-activated. The
hardware-generated LCALL pushes the contents of the program counter onto the stack (but it does
not save the PSW) and reloads the program counter with an address that depends on the source of
the interrupt being vectored too.
Execution proceeds from that location until the RETI instruction is encountered. The RETI
instruction informs the processor that the interrupt routine is no longer in progress, then pops the
two top bytes from the stack and reloads the program counter. Execution of the interrupted program
continues from the point where it was stopped. Note that the RETI instruction is very important
because it informs the processor that the program left the current interrupt priority level. A simple
RET instruction would also have returned execution to the interrupted program, but it would have
left the interrupt control system thinking an interrupt was still in progress. In this case no interrupt of
the same or lower priority level would be acknowledged.
7.4 External Interrupts
The external interrupts 0 and 1 can be programmed to be level-activated or negative-transition
activated by setting or clearing bit IT0 or IT1, respectively, in register TCON. If ITx = 0 (x = 0 or 1),
external interrupt x is triggered by a detected low level at the INTx pin. If ITx = 1, external interrupt
x is negative edge-triggered. In this mode, if successive samples of the INTx pin show a high in one
cycle and a low in the next cycle, interrupt request flag IEx in TCON is set. Flag bit IEx then requests
the interrupt.
If the external interrupt 0 or 1 is level-activated, the external source has to hold the request active
until the requested interrupt is actually generated. Then it has to deactivate the request before the
interrupt service routine is completed, or else another interrupt will be generated.
The external timer 2 reload trigger interrupt request flag EXF2 will be activated by a negative
transition at pin P1.1/T2EX but only if bit EXEN2 is set.
Since the external interrupt pins are sampled once in each machine cycle, an input low should be
held for at least 12 oscillator periods to ensure sampling. If the external interrupt is transition-
activated, the external source has to hold the request pin high for at least one cycle, and then hold
it low for at least one cycle to ensure that the transition is recognized so that the corresponding
interrupt request flag will be set (see figure 7-2). The external interrupt request flags will
automatically be cleared by the CPU when the service routine is called.
Semiconductor Group
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