C511_1 Datasheet, PDF (93/128 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Interrupt System
If two interrupt requests of different priority level are received simultaneously, the request of higher
priority is serviced. If requests of the same priority are received simultaneously, an internal polling
sequence determines which request is serviced. Thus within each priority level there is a second
priority structure determined by the polling sequence as shown in table 7-1.
Table 7-1
Priority-within-Level Structure
Interrupt Source
External Interrupt 0,
IE0
Synchronous Serial Channel SSC
Timer 0 Interrupt,
TF0
External Interrupt 1,
IE1
Timer 1 Interrupt,
TF1
Universal Serial Channel, RI or TI
Timer 2 Interrupt,
TF2 or EXF2
Priority
High
↓
Low
A low-priority interrupt in service can itself be interrupted by a high-priority interrupt, but not by
another low-priority interrupt. A high-priority interrupt in service cannot be interrupted by any other
interrupt source.
The interrupt request flags are located in bit-addressable SFR’s as listed in table 7-2.
Table 7-2
Location of Interrupt Sources Request Flags
Interrupt Request Flag
External Interrupt 0,
Timer 0 Interrupt,
External Interrupt 1,
Timer 1 Interrupt,
Universal Serial Channel,
Universal Serial Channel,
Timer 2 Interrupt,
Timer 2 Interrupt,
Synchr. Serial Channel
Synchr. Serial Channel
IE0
TF0
IE1
TF1
RI (C513/C513A/
C513A-H only)
TI (C513/C513A/
C513A-H only)
TF2
EXF2
TC
WCOL
SFR
TCON
TCON
TCON
TCON
SCON
SCON
T2CON
T2CON
SCF
SCF
Address
88H
88H
88H
88H
98H
98H
C8H
C8H
F8H
F8H
Bit-Addr.
89H
8DH
8BH
8FH
98H
99H
CFH
CEH
F8H
F9H
Semiconductor Group
7-6