C511_1 Datasheet, PDF (90/128 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Interrupt System
7.1 Interrupt Structure
A common mechanism is used to generate the various interrupts, each source having its own
request flag(s) located in a special function register (e.g. TCON, T2CON, SCON). When the
peripheral or external source meets the condition for an interrupt, the dedicated request flag is set,
whether an interrupt is enabled or not. For example, each timer 0 overflow sets the corresponding
request flag TF0. If it is already set, it retains a one (1). But the interrupt is not necessarily serviced.
Now each interrupt requested by the corresponding flag can individually be enabled or disabled by
the enable bits in SFR IE. This determines whether the interrupt will actually be performed. In
addition, there is a global enable bit for all interrupts which, when cleared, disables all interrupts
independent of their individual enable bits.
Table 8-1
Interrupt Sources and Vectors
Source (Request Flags)
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
SSCI
Vector
Vector Address
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
USART serial port interrupt,
(C513/C513A/C513A-H only)
Timer 2 interrupt
(C513/C513A/C513A-H only)
Synchronous serial channel
interrupt (SSC)
0003H
000BH
0013H
001BH
0023H
002BH
0043H
Semiconductor Group
7-3