C511_1 Datasheet, PDF (30/128 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

External Bus Interface
4.1.2 Timing
The timing of the external bus interface, in particular the relationship between the control signals
ALE, PSEN, RD, WR and information on port 0 and port 2, is illustrated in figure 4-11 a) and b).
Data memory:
in a write cycle, the data byte to be written appears on port 0 just before WR is
activated and remains there until after WR is deactivated. In a read cycle, the
incoming byte is accepted at port 0 before the read strobe is deactivated.
Program memory: Signal PSEN functions as a read strobe.
4.1.3 External Program Memory Access
The external program memory is accessed under two conditions:
– whenever signal EA is active or
– whenever EA is high and the program counter (PC) contains an address that is higher than the
internal ROM size.
This requires ROM-less versions of the SAB-C511/513 family components to have EA wired to
ground to allow the program to be fetched from external memory only.
When the CPU is executing out of external program memory, all 8 bits of port 2 are dedicated to an
address output function and may not be used for general-purpose I/O. The contents of the port 2
SFR however is not affected. During external program memory fetches port 2 lines output the high
byte of the PC, and during accesses to external data memory they output either DPH or the port 2
SFR (depending on whether the external data memory access is a MOVX @DPTR or a MOVX
@Ri).
4.2 PSEN - Program Store Enable
The read strobe for external fetches is PSEN. PSEN is not activated for internal fetches. When the
CPU is accessing external program memory, PSEN is activated twice every cycle (except during a
MOVX instruction) no matter whether or not the byte fetched is actually needed for the current
instruction. When PSEN is activated its timing is not the same as for RD. A complete RD cycle,
including activation and deactivation of ALE and RD, takes 12 oscillator periods. A complete PSEN
cycle, including activation and deactivation of ALE and PSEN takes 6 oscillator periods. The
execution sequence for these two types of read cycles is shown in figure 4-11 a) and b).
4.3 ALE - Address Latch Enable
The main function of ALE is to provide a properly timed signal to latch the low byte of an address
from P0 into an external latch during fetches from external memory. The address byte is valid at the
negative transition of ALE. For that purpose, ALE is activated twice every machine cycle. This
activation takes place even if the cycle involves no external fetch. The only time no ALE pulse
comes out is during an access to external data memory when RD/WR signals are active. The first
ALE of the second cycle of a MOVX instruction is missing (see figure 4-11 b). Consequently, in any
system that does not use data memory, ALE is activated at a constant rate of 1/6 of the oscillator
frequency and can be used for external clocking or timing purposes. In systems that do not use
external memory at all and do not use ALE as clock, external ALE generation can be suppressed by
resetting the EALE bit in the SYSCON register. This can help to reduce system RFI. Because ALE
Semiconductor Group
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