HYB39S16400 Datasheet, PDF (7/22 Pages) Siemens Semiconductor Group – 16 MBit Synchronous DRAM

HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
CKE
CKE Buffer
CLK
CLK Buffer
A0
A1
A2
12
A3
A4
A5
A6
A7
12
A8
A9
A10
A11 (BS)
CS
CS Buffer
RAS
RAS Buffer
CAS
CAS Buffer
WE
WE Buffer
Self
Refresh Clock
Row Decoder
Row
Address
Counter
Bank A
Row/Column
Select
11
Predecode A
3 ^Sequential
Control
Bank A
11
Mode Register
3 ^Sequential
Control
Bank B
11
Predecode B
Bank B
Row/Column
Select
2048
8
2048 x 512
Memory Bank A
512
Sense Amplifiers
8
Column Decoder
and DQ Gate
8
8
Data Latches
8
8
8
Data Latches
8
8
Column Decoder
and DQ Gate
Sense Amplifiers
8
512
DQM
DQM Buffer
Row Decoder
Memory Bank B
2048 x 512
2048
Block Diagram for HYB 39S16800T (2 banks × 1 M × 8 SDRAM)
8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
SPB02836
Semiconductor Group
7
1998-10-01