HYB39S16400 Datasheet, PDF (20/22 Pages) Siemens Semiconductor Group – 16 MBit Synchronous DRAM

HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Clock Frequency and Latency
Parameter
Clock frequency
Clock Cycle time
CAS latency
Row to Column delay
RAS latency
Row Active time
Row Precharge time
Row Cycle time
Last Data-In to Precharge (Write Recovery)
Last Data-In to Active/Refresh
Bank to Bank delay time
CAS to CAS delay time
Write latency
DQM Write Mask latency
DQM Data Disable latency
Clock Suspend latency
Symbol
Speed Sort
-8
-10
max. t_CK
125 83 100 66
min. t_CK
8 12 10 15
min. t_AA
3232
min. t_RCD
3232
min. t_RL
6464
min. t_RAS
5353
max. t_RAS
120 120 120 120
min. t_RP
3232
min. t_RC
8585
min. t_DPL
2121
min. t_DPL + t_RP 5
3
5
3
min. t_RRD
2 22 2
min. t_CCD
1111
fixed t_WL
0000
fixed t_DQW
0000
fixed t_DQZ
2222
fixed t_CSL
1111
Unit
MHz
ns
CLK
CLK
CLK
CLK
µs
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Semiconductor Group
20
1998-10-01