HYB39S16400 Datasheet, PDF (12/22 Pages) Siemens Semiconductor Group – 16 MBit Synchronous DRAM

HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
DQM Function
DQM has two functions for data I/O read write operations. During reads, when it turns to high at a
clock timing, data outputs are disabled and become high impedance after two clock delay (DQM
Data Disable Latency t_DQZ). It also provides a data mask function for writes. When DQM is activated,
the write operation at the next clock is prohibited (DQM Write Mask Latency t_DQW = zero clocks).
Suspend Mode
During normal access mode, CKE is held high and CLK is enabled. When CKE is low, it freezes the
internal clock and extends data read and write operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency t_CSL).
Power Down
In order to reduce standby power consumption, a power down mode is available. Bringing CKE low
enters the power down mode and all of receiver circuits are gated. All banks must be precharged
before entering this mode. One clock delay is required for mode entry and exit. The Power Down
mode does not perform any refresh operation.
Auto Precharge
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS
timing accepts one extra address, CA10, to determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function
is initiated. The SDRAM automatically enters the precharge operation one clock after the Read
Command is registered for CAS latencies of 1 and 2, and two clocks for CAS latencies of 3. If
CAS10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated.
The SDRAM automatically enters the precharge operation one clock delay form the last data-in for
CAS latencies of 1 and 2 and two clocks for CAS latencies of 3. This delay is referenced as t_DPL.
Precharge Command
If CA10 is low, the chip needs another way to precharge. In this mode, a separate precharge
command is necessary. When RAS and WE are low and CAS is high at a clock timing, it triggers the
precharge operation. Two address bits, A10 and A11, are used to define banks as shown in the
following list. The precharge command may be applied coincident with the last of burst reads for
CAS Latency = 1 and with the second to the last read data for CAS Latencies = 2 & 3. Writes
require a time t_DPL from the last burst data to apply the precharge command.
Semiconductor Group
12
1998-10-01