HYB39S16400 Datasheet, PDF (15/22 Pages) Siemens Semiconductor Group – 16 MBit Synchronous DRAM

HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Operating Currents
T_A = 0 to 70 ^oC, V_CC = 3.3 V ± 0.3 V
(Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol Test Condition
CAS -8 -10 Unit Note
Latency _{max. max.}
Operating current I_CC1
Burst Length = 4
1
t_RC ≥ t_RC(MIN.)
2
t_CK ≥ t_CK(MIN.), I_O = 0 mA
3
2 bank interleave operation
80 65 mA ^{6, 7}
115 90 mA
125 100 mA
Precharge
I_CC2P
Standby current in
Power Down
Mode
I_CC2PS
CKE ≤ V_IL(MAX.), t_CK ≥ t_CK(MIN.) –
CKE ≤ V_IL(MAX.), t_CK = infinite –
3 3 mA
2 2 mA
Precharge
I_CC2N
Standby current in
Non-power down
Mode
I_CC2NS
CKE ≥ V_IH(MIN.),
–
t_CK ≥ t_CK(MIN.) input signals
changed once in 3 cycles
CKE ≥ V_IH(MIN.), t_CK = infinite, –
input signals are stable
20 20 mA CS = High
10 10 mA
Active Standby
current in Power
Down Mode
I_CC3P
I_CC3PS
CKE ≤ V_IL(MAX)., t_CK ≥ t_CK(MIN.) –
CKE ≤ V_IL(MAX.),
–
t_CK = infinite, input signals
are stable
3 3 mA
2 2 mA
Active Standby
current in Non-
power Down
Mode
Burst Operating
current
Auto (CBR)
Refresh current
Self Refresh
I_CC3N
I_CC3NS
I_CC4
I_CC5
I_CC6
CKE ≥ V_IH(MIN.),
–
t_CK ≥ t_CK(MIN.), changed once
in 3 cycles
CKE ≥ V_IH(MIN.),
–
t_CK = infinite, input signals
are stable
Burst Length = full page 1
t_RC = infinite
2
t_CK ≥ t_CK(MIN.), I_O = 0 mA
3
2 banks activated
t_RC ≥ t_RC(MIN.)
1
2
3
CKE ≤ 0.2 V
–
25 25 mA CS = High
6
15 15 mA
50 40
80 65
120 95
mA ^{6, 7}
75 60
95 75
115 90
22
mA ^{6, 7}
mA
mA
mA ^{6, 7}
Semiconductor Group
15
1998-10-01