HYB39S16400 Datasheet, PDF (13/22 Pages) Siemens Semiconductor Group – 16 MBit Synchronous DRAM

HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Bank Selection by Address Bits
A10
A11
Bank A only
Low
Low
Bank B only
Low
High
Both A and B
High
Don’t Care
Burst Termination
Once a burst read or write operation has been initiated, there are several methods in which to
terminate the burst operation prematurely. These methods include using another Read or Write
Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst
cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst
operation but leave the bank open for future Read or Write Commands to the same page of the
active bank. When interrupting a burst with another Read or Write Command care must be taken to
avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the
easiest method to use when terminating a burst operation before it has been completed. If a Burst
Stop command is issued during a burst write operation, then any residual data from the burst write
cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is
registered will be written to the memory.
Power Up Procedure
All V_DD and V_DDQ must reach the specified voltage no later than any of input signal voltages. An
initial pause of 200 µs is required after power on. All banks have to be precharged and a minimum
of 2 auto-refresh cycles are required prior to the mode register set operation.
Semiconductor Group
13
1998-10-01