HYB39S16400 Datasheet, PDF (11/22 Pages) Siemens Semiconductor Group – 16 MBit Synchronous DRAM

HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Read and Write Access Mode
When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle
starts. According to address data, a word line of the selected bank is activated and all of sense
amplifiers associated to the word line are fired. A CAS cycle is triggered by setting RAS high and
CAS low at a clock timing after a necessary delay, t_RCD, from the RAS timing. WE is used to define
either a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 125 MHz data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page. Column
addresses are segmented by the burst length and serial data accesses are done within this
boundary. The first column address to be accessed is supplied at the CAS timing and the
subsequent addresses are generated automatically by the programmed burst length and its
sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’,
then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
Full page burst operation is only possible using the sequential burst type and page length is a
function of the I/O organisation and column addressing. Full page burst operation do not self
terminate once the burst length has been reached. In other words, unlike burst length of 2, 3 or 8,
full page burst continues until it is terminated using another command.
Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column
address are possible once the RAS cycle latches sense amplifiers. The maximum t_RAS or the refresh
interval time limits the number of random column accesses. A new burst access can be done even
before the previous burst ends. The interrupt operation at every clock cycles is supported. When the
previous burst is interrupted, the remaining addresses are overridden by the new address with the
full burst length. An interrupt which accompanies with an operation change from a read to a write is
possible by exploiting DQM to avoid bus contention.
When two banks are activated sequentially, interleaved bank read or write operations are possible.
With the programmed burst length, alternate access and precharge operations on two banks can
realize fast serial data access modes among many different pages. Once two banks are activated,
column to column interleave operation can be done between two different pages.
Refresh Mode
SDRAM has two refresh modes, a CAS-before-RAS (CBR) automatic refresh and a self refresh. All
of banks must be precharged before applying any refresh mode. An on-chip address counter
increments the word and the bank addresses and no bank information is required for both refresh
modes. The chip enters the automatic refresh mode, when RAS and CAS are held low and CKE and
WE are held high at a clock timing. The mode restores word line after the refresh and no external
precharge command is necessary. A minimum t_RC time is required between two automatic
refreshes in a burst refresh mode. The same rule applies to any access command after the
automatic refresh operation.
The chip has an on-chip timer and the self refresh mode is available. It enters the mode when RAS,
CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the
clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation.
After the exit command, at least one t_RC delay is required prior to any access command.
Semiconductor Group
11
1998-10-01