HYB39S16400 Datasheet, PDF (5/22 Pages) Siemens Semiconductor Group – 16 MBit Synchronous DRAM

HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Signal Pin Description (cont’d)
Pin
Type Signal Polarity Function
DQM
LDQM
UDQM
Input
Pulse Active
High
The Data Input/Output mask places the DQ buffers in a
high impedance state when sampled high. In Read mode,
DQM has a latency of two clock cycles and controls the
output buffers like an output enable. In Write mode, DQM
has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the
write operation if DQM is high.
V_DD
Supply –
–
V_SS
V_DDQ
Supply –
–
V_SSQ
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to
provide improved noise immunity.
Semiconductor Group
5
1998-10-01