C161RI_1 Datasheet, PDF (63/317 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontroller

The Central Processing Unit (CPU)
C161RI
Internal RAM
Context
Pointer
R15
(CP) + 30
R14
(CP) + 28
R13
R12
R11
R10
R9
R8
R7
...
R6
R5
R4
R3
R2
R1
(CP) + 2
R0
(CP)
Figure 4-7
Register Bank Selection via Register CP
MCD02003
Several addressing modes use register CP implicitly for address calculations. The addressing
modes mentioned below are described in chapter “Instruction Set Summary”.
Short 4-Bit GPR Addresses (mnemonic: Rw or Rb) specify an address relative to the memory
location specified by the contents of the CP register, i.e. the base of the current register bank.
Depending on whether a relative word (Rw) or byte (Rb) GPR address is specified, the short 4-bit
GPR address is either multiplied by two or not before it is added to the content of register CP (see
figure below). Thus, both byte and word GPR accesses are possible in this way.
GPRs used as indirect address pointers are always accessed wordwise. For some instructions only
the first four GPRs can be used as indirect address pointers. These GPRs are specified via short 2-
bit GPR addresses. The respective physical address calculation is identical to that for the short 4-
bit GPR addresses.
Short 8-Bit Register Addresses (mnemonic: reg or bitoff) within a range from F0_H to FF_H interpret
the four least significant bits as short 4-bit GPR address, while the four most significant bits are
ignored. The respective physical GPR address calculation is identical to that for the short 4-bit GPR
addresses. For single bit accesses on a GPR, the GPR's word address is calculated as just
described, but the position of the bit within the word is specified by a separate additional 4-bit value.
Semiconductor Group
4-23
1998-05-01