C161RI_1 Datasheet, PDF (22/317 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontroller

Architectural Overview
C161RI
Hardware detection of the selected memory space is placed at the internal memory decoders and
allows the user to specify any address directly or indirectly and obtain the desired data without using
temporary registers or special instructions.
A 2 KByte 16-bit wide on-chip XRAM provides fast access to user data (variables), user stacks
and code. The on-chip XRAM is realized as an X-Peripheral and appears to the software as an
external RAM. Therefore it cannot store register banks and is not bitaddressable. The XRAM allows
16-bit accesses with maximum speed.
For Special Function Registers 1024 Bytes of the address space are reserved. The standard
Special Function Register area (SFR) uses 512 bytes, while the Extended Special Function
Register area (ESFR) uses the other 512 bytes. (E)SFRs are wordwide registers which are used for
controlling and monitoring functions of the different on-chip units. Unused (E)SFR addresses are
reserved for future members of the C166 family with enhanced functionality.
External Bus Interface
In order to meet the needs of designs where more memory is required than is provided on chip, up
to 8 MBytes of external RAM and/or ROM can be connected to the microcontroller via its external
bus interface. The integrated External Bus Controller (EBC) allows to access external memory and/
or peripheral resources in a very flexible way. For up to five address areas the bus mode
(multiplexed / demultiplexed), the data bus width (8-bit/16-bit) and even the length of a bus cycle
(waitstates, signal delays) can be selected independently. This allows to access a variety of
memory and peripheral components directly and with maximum efficiency. If the device does not
run in Single Chip Mode, where no external memory is required, the EBC can control external
accesses in one of the following external access modes:
• 16-/18-/20-/23-bit Addresses, 16-bit Data, Demultiplexed
• 16-/18-/20-/23-bit Addresses, 8-bit Data, Demultiplexed
• 16-/18-/20-/23-bit Addresses, 16-bit Data, Multiplexed
• 16-/18-/20-/23-bit Addresses, 8-bit Data, Multiplexed
The demultiplexed bus modes use PORT1 for addresses and PORT0 for data input/output. The
multiplexed bus modes use PORT0 for both addresses and data input/output. Port 4 is used for the
upper address lines (A16 …) if selected.
Important timing characteristics of the external bus interface (waitstates, ALE length and Read/
Write Delay) have been made programmable to allow the user the adaption of a wide range of
different types of memories and/or peripherals. Access to very slow memories or peripherals is
supported via a particular ’Ready’ function.
For applications which require less than 64 KBytes of address space, a non-segmented memory
model can be selected, where all locations can be addressed by 16 bits, and thus Port 4 is not
needed as an output for the upper address bits (Axx … A16), as is the case when using the
segmented memory model.
The on-chip XBUS is an internal representation of the external bus and allows to access integrated
application-specific peripherals/modules in the same way as external components. It provides a
defined interface for these customized peripherals.
The on-chip XRAM and the on-chip I²C-Module are examples for these X-Peripherals.
Semiconductor Group
2-8
1998-05-01