C161RI_1 Datasheet, PDF (264/317 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontroller

Power Management
C161RI
19 Power Management
For an increasing number of microcontroller based systems it is an important objective to reduce the
power consumption of the system as much as possible. A contradictory objective is, however, to
reach a certain level of system performance. Besides optimization of design and technology a
microcontroller’s power consumption can generally be reduced by lowering its operating frequency
and/or by reducing the circuitry that is clocked. The architecture of the C161RI provides three major
means of reducing its power consumption (see figure below) under software control:
q Reduction of the CPU frequency for Slow Down operation (Flexible Clock Gen. Management)
q Selection of the active peripheral modules (Flexible Peripheral Management)
q Special operating modes to deactivate CPU, port drivers and control logic (Idle, Power Down)
This enables the application (i.e. the programmer) to choose the optimum constellation for each
operating condition, so the power consumption can be adapted to conditions like maximum
performance, partial performance, intermittend operation or standby.
Intermittend operation (i.e. alternating phases of high performance and power saving) is supported
by the cyclic interrupt generation mode of the on-chip RTC (real time clock).
Power
f_CPU
Figure 19-1
Power Reduction Possibilities
Semiconductor Group
19-1
Active
Idle
Power ^Down
No. of act.
Peripherals
1998-05-01