C161RI_1 Datasheet, PDF (100/317 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontroller

Clock Generation
C161RI
The internal operation of the C161RI is controlled by the internal CPU clock f_CPU. Both edges of the
CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations (see figure
below).
Direct Clock Drive
f_XTAL
f_CPU
Prescaler Operation
f_XTAL
f_CPU
SDD Operation
f_XTAL
f_CPU
TCL TCL
TCL TCL
TCL
TCL
Figure 6-5
Generation Mechanisms for the CPU Clock
Direct Drive
When direct drive is configured (CLKCFG = ’011’) the C161RI’s clock system is directly fed from the
external clock input, i.e. f_CPU = f_OSC. This allows operation of the C161RI with a reasonably small
fundamental mode crystal. The specified minimum values for the CPU clock phases (TCLs) must be
respected. Therefore the maximum input clock frequency depends on the clock signal’s duty cycle.
Prescaler Operation
When prescaler operation is configured (CLKCFG = ’001’) the C161RI’s input clock is divided by 2
to generate then CPU clock signal, i.e. f_CPU = f_OSC/2. This requires the oscillator (or input clock) to
run on 2 times the intended operating frequency but guarantees a 50% duty cycle for the internal
clock system independent of the input clock signal’s waveform.
Semiconductor Group
6-4
1998-05-01