C161RI_1 Datasheet, PDF (147/317 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontroller

The External Bus Interface
C161RI
Read/Write Signal Delay
The C161RI allows the user to adjust the timing of the read and write commands to account for
timing requirements of external peripherals. The read/write delay controls the time between the
falling edge of ALE and the falling edge of the command. Without read/write delay the falling edges
of ALE and command(s) are coincident (except for propagation delays). With the delay enabled, the
command(s) become active half a CPU clock (1 TCL) after the falling edge of ALE.
The read/write delay does not extend the memory cycle time, and does not slow down the controller
in general. In multiplexed bus modes, however, the data drivers of an external device may conflict
with the C161RI’s address, when the early RD signal is used. Therefore multiplexed bus cycles
should always be programmed with read/write delay.
Segment
ALE
BUS (P0)
RD
Bus Cycle
Address
1)
Data/Instr.
BUS (P0)
Address
Data
WR
Read/Write
Delay
1) _{The Data drivers from the previous bus cycle should be disabled when the RD signal becomes active.}
MCT02066
Figure 9-9
Read/Write Delay
The read/write delay is controlled via the RWDCx bits in the BUSCON registers. The command(s)
will be delayed, if bit RWDCx is ‘0’ (default after reset).
Semiconductor Group
9-14
1998-06-01