C161RI_1 Datasheet, PDF (131/317 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontroller

Dedicated Pins
C161RI
8 Dedicated Pins
Most of the input/output or control signals of the functional the C161RI are realized as alternate
functions of pins of the parallel ports. There is, however, a number of signals that use separate pins,
including the oscillator, special control signals and, of course, the power supply.
The table below summarizes the 21 dedicated pins of the C161RI.
Pin(s)
ALE
RD
WR/WRL
READY
EA
NMI
XTAL1, XTAL2
RSTIN
RSTOUT
VAREF, VAGND
VDD, VSS
Function
Address Latch Enable
External Read Strobe
External Write/Write Low Strobe
Ready Input
External Access Enable
Non-Maskable Interrupt Input
Oscillator Input/Output
Reset Input
Reset Output
Power Supply for Analog/Digital Converter
Digital Power Supply and Ground (6 pins each)
The Address Latch Enable signal ALE controls external address latches that provide a stable
address in multiplexed bus modes.
ALE is activated for every external bus cycle independent of the selected bus mode, i.e. it is also
activated for bus cycles with a demultiplexed address bus. When an external bus is enabled (one
or more of the BUSACT bits set) also X-Peripheral accesses will generate an active ALE signal.
ALE is not activated for internal accesses, i.e. accesses to ROM/OTP/Flash (if provided), the
internal RAM and the special function registers. In single chip mode, i.e. when no external bus is
enabled (no BUSACT bit set), ALE will also remain inactive for X-Peripheral accesses.
During reset an internal pulldown ensures an inactive (low) level on the ALE output.
The External Read Strobe RD controls the output drivers of external memory or peripherals when
the C161RI reads data from these external devices. During accesses to on-chip X-Peripherals RD
remains inactive (high).
During reset an internal pullup ensures an inactive (high) level on the RD output.
The External Write Strobe WR/WRL controls the data transfer from the C161RI to an external
memory or peripheral device. This pin may either provide an general WR signal activated for both
byte and word write accesses, or specifically control the low byte of an external 16-bit device (WRL)
together with the signal WRH (alternate function of P3.12/BHE). During accesses to on-chip
X-Peripherals WR/WRL remains inactive (high).
During reset an internal pullup ensures an inactive (high) level on the WR/WRL output.
Semiconductor Group
8-1
1998-05-01