C161RI_1 Datasheet, PDF (50/317 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontroller

The Central Processing Unit (CPU)
C161RI
4.3 Instruction State Times
Basically, the time to execute an instruction depends on where the instruction is fetched from, and
where possible operands are read from or written to. The fastest processing mode of the C161RI is
to execute a program fetched from the internal code memory. In that case most of the instructions
can be processed within just one machine cycle, which is also the general minimum execution time.
All external memory accesses are performed by the C161RI’s on-chip External Bus Controller
(EBC), which works in parallel with the CPU.
This section summarizes the execution times in a very condensed way. A detailed description of the
execution times for the various instructions and the specific exceptions can be found in the
“C16x Family Instruction Set Manual”.
The table below shows the minimum execution times required to process a C161RI instruction
fetched from the internal code memory, the internal RAM or from external memory. These execution
times apply to most of the C161RI instructions - except some of the branches, the multiplication, the
division and a special move instruction. In case of internal ROM program execution there is no
execution time dependency on the instruction length except for some special branch situations. The
numbers in the table are in units of CPU clock cycles and assume no waitstates.
Minimum Execution Times
Memory Area
Internal code memory
Internal RAM
16-bit Demux Bus
16-bit Mux Bus
8-bit Demux Bus
8-bit Mux Bus
Instruction Fetch
Word
Instruction
Doubleword
Instruction
2
2
6
8
2
4
3
6
4
8
6
12
Word Operand Access
Read from
Write to
2
---
0/1
0
2
2
3
3
4
4
6
6
Execution from the internal RAM provides flexibility in terms of loadable and modifiable code on the
account of execution time.
Execution from external memory strongly depends on the selected bus mode and the programming
of the bus cycles (waitstates).
The operand and instruction accesses listed below can extend the execution time of an instruction:
• Internal code memory operand reads (same for byte and word operand reads)
• Internal RAM operand reads via indirect addressing modes
• Internal SFR operand reads immediately after writing
• External operand reads
• External operand writes
• Jumps to non-aligned double word instructions in the internal ROM space
• Testing Branch Conditions immediately after PSW writes
Semiconductor Group
4-10
1998-05-01