SDA9280 Datasheet, PDF (21/43 Pages) Siemens Semiconductor Group – ICs for Consumer Electronics

SDA 9280 B22
To achieve an optimal PLL operation an adaption to the required frequency range can
be programmed (Ι²C signal: PLLRAN).
2.11 Input-Output Signal Delay Time
Due to several digital signal processing stages transients of the digital input signal at the
YUV inputs appear with a certain delay at the analog YUV outputs. In the following table
are defined the values for two typical circuit configurations. The configuration of the
circuit is defined as the total configuration of all programmable signal processing stages
on the device, the programming itself is performed via the Ι²C Bus.
Name
Internal PLL
Compander
Oversampling
Input data format
Zoom
Internal PLL
Compander
Oversampling
Input data format
Zoom
Function
Time delay
Switched OFF
(Subaddress 10_H, Bit D5 ... D0 = 00 0000)
Bypassed
(Subaddress 06_H, Bit D1 = 0)
No
(Subaddress 07_H, Bit D1 ... D0 = 00)
(Subaddress 00_H, Bit D5 ... D4 = 01 or 10
or 11)
120 CLL typ
No
(frequency of SCA and CLL is identical)
Switched ON
(Subaddress 10_H, Bit D5 ... D0 = 00 0010)
(Subaddress 14_H, Bit D7 ... D0 = 0100 0100)
Active without compression or expansion
(Subaddress 06_H, Bit D0 = 0)
(Subaddress 06_H, Bit D7 ... D2 = 000001)
Yes
(Subaddress 07_H, Bit D1 ... D0 = 11)
(Subaddress 00_H, Bit D5 ... D4 = 01 or 10 or
11)
126 CLL typ
No
(frequency of SCA and CLL is identical)
Semiconductor Group
21
1998-02-01