SDA9280 Datasheet, PDF (12/43 Pages) Siemens Semiconductor Group – ICs for Consumer Electronics

SDA 9280 B22
The representation of the samples is programmable separately for luminance and
chrominance signals as positive dual code or 2’s complement code
(Ι²C signals: INCODL, INCODC)
The amplitude resolution for each input is 8 Bit, the maximal clock frequency is 30 MHz.
Consequently the SDA 9280 is dedicated for applications in high quality digital video
systems. The data input stages and the internal data multiplexer operate with a special
data input clock (SCA). For applications in the Siemens MEGAVISION^® System the
SCA-clock is identical with the memory output clock. A separation of the data input clock
and the system clock is relevant to handle the special data format occurring at “zoom”
operation mode. For other applications SCA can be connected with CLL.
Note: Zoom mode causes a greater signal delay time of the whole IC. Zoom mode
identification is performed automatically.
2.2 Chrominance Interpolation (Interpolator 1)
10
UED10246
dB
0
-10
-20
-30
-40
-50
0
0.1
0.2
0.3
0.4
0.5
f
f_S
Figure 3
Frequency Response of a Filter Stage of Interpolator 1
(ƒ_s is the sampling frequency at the output of the interpolation filter stage)
For internal processing the 4:4:4 parallel format is used. The 4:1:1 data are interpolated
by two interpolation filters having the same frequency response (see figure 3) to the
4:4:4 format. Each filter performs a doubling of the sample frequency. The 4:4:4
interpolation of 4:2:2 data is done by the second filter stage. The diagram shows the
frequency response of one filter stage.
Semiconductor Group
12
1998-02-01