SDA9280 Datasheet, PDF (20/43 Pages) Siemens Semiconductor Group – ICs for Consumer Electronics

SDA 9280 B22
and DIVVCO must be set according to the respective oversampling frequency. The
reference clock of the PLL is the system clock CLL. The output frequency of the PLL
f_OUTPUT is calculated by the following equation:
* * ^{f f OUTPUT = REFERENCE (2 DIVVCO) / DIVREF}
Note: An arbitrary setting of the output frequency is not allowed. It has to be observed
that there is resulting an integer number of clock periods per line. E.g. the input
signal has 858 clock periods per line, 3:4 signal expansion results in
858 _* 3/4 = 643.5 clock periods per line, which is not an integer number.
Therefore this adjustment results in phase jumps of the output clock and in an
unstable working condition of the PLL.
The following table gives an overview of possible PLL modes referred to an input signal
with 864 pixels per line and a clock frequency of 13.5 MHz.
Compression-/ Resulting
Expansion- Clock
Factor
Periods per
Line
4:3
1152
5:4
1080
11:9
1056
7:6
1008
9:8
972
10:9
960
13:12
936
1:1
864
15:16
810
11:12
792
8:9
768
7:8
756
5:6
720
13:16
702
7:9
672
3:4
648
Compander
Read
Frequency
[MHz]
18
16.875
16.5
15.75
15.1875
15
14.625
13.5
12.65625
12.375
12
11.8125
11.25
10.96875
10.5
10.125
DIVVCO
4
5
11
7
9
10
13
4
15
11
8
7
5
13
7
3
DIVREF
3
4
9
6
8
9
12
4
16
12
9
8
6
16
9
4
The PLL circuit can be switched inactive (Ι²C signal: PLLON). In this mode the system
clock is also used for output processing and D/A conversion.
Semiconductor Group
20
1998-02-01