SDA9280 Datasheet, PDF(19/43 Page) Siemens Semiconductor Group

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SDA9280 Datasheet, PDF (19/43 Pages) Siemens Semiconductor Group – ICs for Consumer Electronics

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SDA 9280 B22

The Full Range Output Current of the Y, U, and V channels (IOFR) is determined by the

current IREF at the RREF pin by

IOFR â (4/3) IREF

The voltage at pin RREF is generated via pin VREF by an internal operational amplifier and

follows the voltage at pin VREF. Thus IREF is given by

IREF â VVREF/RREF

where RREF is a resistor between pin RREF and analog ground. Another way to define IREF

is the application of a current sink at the RREF point. For recommended values of VVREF

and IREF see chapter âRecommended Operation Conditionsâ. For applications with lower

requirements there is still another way to define IOFR: Connect pin VREF to the positive

supply and apply a resistor against ground. Since in this operation mode the internal

reference amplifier goes into saturation, the exact value of IREF is not so well predictable

2.10 PLL Circuit

Divider

DIVVCO

Reference

Clock

Divider

DIVREF

Ã·2

Phase

Discriminator

VCO

Output

Clock

UES10250

Figure 7

The internal PLL supplies the clock signals needed for compander operation, output

processing and D/A conversion. The output frequency of the PLL is defined by

programming the divider factors of the reference clock and of the VCO clock

(Î2C signals: DIVREF, DIVVCO). The PLL always supplies the frequency needed for

oversampling. The clocks used in the other output processing parts are derived from this

oversampling clock. Even if no oversampling is programmed (OVSAMP = 0) DIVREF

Semiconductor Group

1998-02-01

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