SDA9280 Datasheet, PDF (16/43 Pages) Siemens Semiconductor Group – ICs for Consumer Electronics

SDA 9280 B22
This realization does not effect the horizontal detail resolution of the picture because no
filtering is executed.
The highest read frequency is 4/3 of the CLL-frequency for signal compression, the
lowest is 3/4 of the CLL-frequency for signal expansion. The reading clock is supplied by
the internal PLL.
The compander operation mode is programmable via Ι²C signals COMP and COMEX.
Note: Positioning of a 4:3-signal on a 16:9-screen is realized by delaying the HS-signal.
HS also controls the deflection circuit. In the Siemens MEGAVISION^® System a
programmable HS-delay is available in the Memory Sync Controller (MSC) circuit.
2.7 Oversampling, Interpolator 2
10
UED10249
dB
0
-10
-20
-30
-40
-50
0
0.1
0.2
0.3
0.4
0.5
f / f_S
Figure 6
Frequency Response of Interpolator 2
(ƒ_s is the sampling frequency at the output of the interpolation filter)
In general D/A conversion requires postfiltering to avoid non-harmonic distortions
caused by intermodulations of the signal with its spectral images. These
intermodulations may come from non-linear characteristics of subsequent amplifier
stages or of the display. The spectral images are duplicates of the signal spectrum
around multiples of the sampling frequency. These images, a counterpart of aliasing in
the A/D conversion, become visible after D/A conversion. They are only reduced by the
sinx/x characteristic of the D/A converter.
Semiconductor Group
16
1998-02-01