GS4900B Datasheet, PDF (79/102 Pages) Semtech Corporation – SD Clock and Timing Generator with GENLOCK

Table 3-13: Configuration and Status Registers (Continued)
Register Name
ASR_SEL[2:0]
(GS4901B only)
RSVD
Audio_Cap_Genlock
(GS4901B only)
Audio_Res_Genlock
(GS4901B only)
RSVD
ACLK1_fs_Multiple
(GS4901B only)
Address
32h
32h
33h - 38h
39h
39h
3Ah
3Ah
3Bh-3Eh
3Fh
3Fh
Bit
15-3
2-0
–
15-6
5-0
15-6
5-0
–
15-3
2-0
Description
R/W
Reserved. Set these bits to zero when writing to
–
32h.
Replaces the external ASR_SEL[2:0] pins when
R/W
Host_ASR_Select (bit 2 of address 31h) is HIGH.
The default setting of this register corresponds to
an audio sample rate of 48kHz.
Reference: Section 3.7.2 on page 54
Reserved.
–
Reserved. Set these bits to zero when writing to
–
39h.
Control signal to adjust loop bandwidth of audio
R/W
genlock block.
The value programmed in this register must be
between 10 and Audio_Res_Genlock - 21.
The default value of this register will depend on the
fundamental sampling frequency selected.
Reference: Section 3.6.2 on page 49
Reserved. Set these bits to zero when writing to
–
3Ah.
Control signal to adjust loop bandwidth of audio
R/W
genlock block.
The value programmed in this register must be
between 32 and 42.
The default value of this register will depend on the
fundamental sampling frequency selected.
Reference: Section 3.6.2 on page 49
Reserved
–
Reserved. Set these bits to zero when writing to
–
3Fh.
The user may set this register to select the desired R/W
frequency of the audio clock on ACLK1 (a multiple
of the fundamental sampling rate, fs). The audio
clock frequency may be set as: 512fs, 384fs, 256fs,
192fs, 128fs, 64fs, fs, or z-bit. See Table 3-8 for more
details.
NOTE: To output a frequency of 348fs or 192fs, bit 5
of register 31h must also be set HIGH.
Reference: Section 3.7.2 on page 54
Default
–
011b
–
–
–
–
–
–
–
0
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
79 of 102