GS4900B Datasheet, PDF(74/102 Page) Semtech Corporation – SD Clock and Timing Generator with GENLOCK

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GS4900B Datasheet, PDF (74/102 Pages) Semtech Corporation – SD Clock and Timing Generator with GENLOCK

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Table 3-13: Configuration and Status Registers (Continued)

Video_Status

RSVD

Address

1Fh

20h-23h

Bit

15-5

Description

Reserved.

Ref_H_Polarity - status register to indicate the

detected H Sync polarity ('1' for positive, '0' for

negative).

This bit will be zero when no reference signal is

present.

Reference: Section 3.4.3 on page 42

Ref_V_Polarity - status register to indicate the

detected V Sync polarity ('1' for positive, '0' for

negative).

This bit will be zero when no reference signal is

present and for digital blanking input references.

Reference: Section 3.4.3 on page 42

Ref_Blank_Timing - status register to indicate the

input detection of H blanking vs. H sync timing (â1â

for blanking, '0' for sync timing).

This bit will be zero when no reference signal is

present.

Reference: Section 3.4.3 on page 42

A_pll_Lock (GS4901B only)- this bit will be HIGH

when the generated audio clock is locked to the

video clock reference.

NOTE: This bit will remain high in the GS4900B.

Reference: bit 1 of register 15h.

V_pll_Lock - this bit will be HIGH when the

generated video clock is locked to the H Sync input

reference.

Reference: bit 1 of register 15h.

Reserved

R/W

Default

N/A

GS4901B/GS4900B SD Clock and Timing Generator

with GENLOCK

Data Sheet

37703 - 4

December 2009

74 of 102

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