GS4900B Datasheet, PDF (69/102 Pages) Semtech Corporation – SD Clock and Timing Generator with GENLOCK

Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Reference_Standard_Disable 13h-11h
RSVD
14h
Bit
38-0
–
Description
R/W
The Reference_Standard_Disable register may be
R/W
used to disable/enable one or more of the input
standards given in Table 1-2 from being recognized
by the device and used to genlock the output. This
is done by setting the bit HIGH that corresponds to
the VID_STD[5:0] value of the video format.
For example, if bit 5 is set HIGH, then the output
clock and timing signals will not genlock to an input
reference with timing corresponding to
VID_STD[5:0] = 5 in Table 1-2.
Likewise, to enable recognition of VID_STD[5:0] =
26 (1080i/59.94) as an input reference format, the
user must set bit 26 LOW.
Address 13h = bits 38-32*
Address 12h = bits 31-16
Address 11h = bits 15-0
*Bits 47-39 of address 13h should always be written
HIGH.
Reference: Section 3.5 on page 43
Reserved
–
Default
FFFFh
FFFFh
F800h
–
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
69 of 102