GS4900B Datasheet, PDF (17/102 Pages) Semtech Corporation – SD Clock and Timing Generator with GENLOCK

Table 1-1: Pin Descriptions (Continued)
Pin
Number
58
Name
SDIN_TDI
59
SDOUT_TDO
60
CS_TMS
61
RESET
Timing
Type Description
Synchronous
with
SCLK_TCLK
Input
SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Input / Test Data Input.
Host Mode (JTAG/HOST = LOW):
SDIN_TDI operates as the host interface serial input, SDIN, used to
write address and configuration information to the internal
registers of the device.
JTAG Test Mode (JTAG/HOST = HIGH):
SDIN_TDI operates as the JTAG test data input, TDI.
Synchronous
with
SCLK_TCLK
Output
SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Output / Test Data Output.
Host Mode (JTAG/HOST = LOW):
SDOUT_TDO operates as the host interface serial output, SDOUT,
used to read status and configuration information from the internal
registers of the device.
JTAG Test Mode (JTAG/HOST = HIGH):
SDOUT_TDO operates as the JTAG test data output, TDO.
Synchronous
with
SCLK_TCLK
Input
SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Chip Select / Test Mode Select.
Host Mode (JTAG/HOST = LOW):
CS_TMS operates as the host interface chip select, CS, and is active
LOW.
JTAG Test Mode (JTAG/HOST = HIGH):
CS_TMS operates as the JTAG test mode select, TMS, and is active
HIGH.
Non
Input
Synchronous
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to their default
settings or to reset the JTAG test sequence.
Host Mode (JTAG/HOST = LOW):
When asserted LOW, all host registers and functional blocks will be
set to their default conditions. All input and output signals will
become high impedance, except PCLK1 and PCLK2, which will be set
LOW.
When set HIGH, normal operation of the device will resume.
The user must hold this pin LOW during power-up and for a
minimum of 500 uS after the last supply has reached its operating
voltage.
JTAG Test Mode (JTAG/HOST = HIGH):
When asserted LOW, all host registers and functional blocks will be
set to their default conditions and the JTAG test sequence will be
held in reset.
When set HIGH, normal operation of the JTAG test sequence will
resume.
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
17 of 102