GS4900B Datasheet, PDF (70/102 Pages) Semtech Corporation – SD Clock and Timing Generator with GENLOCK

Table 3-13: Configuration and Status Registers (Continued)
Register Name
Genlock_Status
Address
15h
15h
15h
15h
15h
15h
15h
Bit
15-6
5
4
3
2
1
0
Description
R/W
Reserved.
–
Reference_Lock - this bit will be HIGH when the
R
output is successfully genlocked to the input (i.e.
when bits 4-1 of this register are HIGH and are not
masked by bits 4-2 of register 16h).
The LOCK_LOST output pin is an inverted copy of
this bit.
Reference: Section 3.6.1 on page 49
F_Lock - this bit will be HIGH when the output F is R
successfully genlocked to the FSYNC input.
NOTE: If the input reference does not include an
FSYNC input, this bit will have the same setting as
V_Lock (bit 3).
Reference: Section 3.6.1 on page 49
V_Lock - this bit will be HIGH when the output V is R
successfully genlocked to the VSYNC input.
Reference: Section 3.6.1 on page 49
H_Lock - this bit will be HIGH when the output H is R
successfully genlocked to the HSYNC input.
Reference: Section 3.6.1 on page 49
Clock_Lock - this bit will be HIGH when the video
R
clock is locked to the internal V_pll AND the audio
clock is locked to the internal A_pll (i.e. bits 0 and 1
of register 1Fh are HIGH).
Reference: Section 3.6.1 on page 49
Reference_Present - this bit will be HIGH when a
R
valid input reference signal has been applied to the
device. The REF_LOST output pin is an inverted copy
of this bit.
Reference: Section 3.5.2 on page 44
Default
–
N/A
N/A
N/A
N/A
N/A
N/A
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
70 of 102