GS4900B Datasheet, PDF (59/102 Pages) Semtech Corporation – SD Clock and Timing Generator with GENLOCK

AFS_OUT
Total Line
Horizontal Sync Output
Line 1 every n frames where:
n = 1 @ 25fps: fs = 32kHz
n = 1 @ 25fps, 30fps & 60fps: fs = 44.1kHz
n = 1 @ 25fps, 30fps & 60fps; fs = 48kHz
n = 2 @ 24fps; fs = 44.1kHz, 48kHz
n = 3 @ 24fps, 30fps & 60fps: fs = 32kHz
n = 5 @ 29.97fps & 59.94fps; fs = 48kHz
n = 15 @ 29.97fps & 59.94fps; fs = 32kHz
n = 100 @ 29.97fps; fs = 44.1kHz
n = 200 @ 59.94fps; fs = 44.1kHz
Figure 3-8: AFS Output Timing
The phasing of the divide by n counter can be controlled by the 10FID input or via
designated registers in the host interface.
By default, the 10FID input pin controls the AFS phase (in addition to controlling the
10FID phase); however, this feature may be disabled by setting bit 0 of the
Audio_Control register (see Section 3.10.3 on page 67). In addition, the AFS signal may
be reset via register 1Ah.
3.8.3 USER_1~4
As described in Table 1-3, the GS4901B/GS4900B offers 4 user programmable output
signals which are available independent of the selected output video format.
Each user signal is individually programmable and the polarity, position, and width of
each output may be defined with respect to the digital output timing of the device. Each
output signal may be programmed in both the horizontal and vertical dimensions
relative to the leading edges of H Blanking and V Blanking. If desired, the pulses
produced may then be combined with a logical AND, OR, or XOR function to produce a
composite signal (for example, a horizontal back porch pulse during active lines only, or
the active part of lines 15 through 20 for vertical information retrieval).
By default, the AND, OR, and XOR functions are disabled. Therefore, when a USER signal
is selected using the Output_Select registers of the host interface, the signal will go LOW
(default polarity) at the H_Start pixel and return HIGH after the H_Stop pixel. Setting the
AND bit HIGH, for example, will cause the USER signal to be active only when USER_H
is active and USER_V is active (i.e. the pixel is between both H_Start and H_Stop and
V_Start and V_Stop). See Figure 3-9.
NOTE: The effective horizontal range of the four user-defined timing signals is [H_Start
+ 1, H_Stop], except when H_Start = 1, in which case the range is [H_Start, H_Stop]. This
prevents the user from specifying an output USER signal that begins on pixel 2 of a line.
In the case of interlaced output formats, the programmed vertical start and stop lines
refer to the start and stop lines of the generated USER signal on the odd fields. The start
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
59 of 102