GX3290 Datasheet, PDF (42/47 Pages) Semtech Corporation – 290 x 290 3.5Gb/s Crosspoint Switch

5.2 Estimated Worst-Case Load Current Steps
Under normal operation, the power supply networks need to minimize voltage
transients due to configuration change related load current steps. When the device reset
is asserted while the device is drawing significant current, the load on power supplies
could be shed fast enough to raise concerns about the board level voltage regulator
dynamics, and the impact of any power supply network inductance.
5.2.1 VCC_25_A Supply
The tail currents of CML blocks (the high-speed signal paths) in the matrix switch
relatively slowly, with worst case switching times of 30ns and typical times ~50ns. The
matrix supply current of ~9.4A could in principle switch in 30ns, but in practice the
propagation delay of UPDATE_EN[7:0] signals across the matrix will increase the
switching time somewhat.
The VCC_25_A supply current drawn by individual EQs takes more than 10ns to rise
upon application of control signals. The VCC_25_A supply current drops in as little as
5ns upon assertion of reset, though, and the reset signal arrival times at EQs in a bank
are roughly uniformly distributed over an interval of 0.8ns. This means that the
VCC_25_A current drawn by all EQs together, ~3.2A, could be shed in 5.8ns.
The trace drivers draw significant current from the VCC_25_A supply, up to ~4.1A total
for all trace drivers together, and this current can rise in as little as 20ns upon the
de-assertion of power-down signals, or fall in as little as 1ns upon the assertion of
power-down or reset signals. The arrival times of power-down or reset signals within
the bottom trace driver bank are nearly uniformly distributed over an interval of 0.8ns,
while the arrival time of power-down or reset signals within the top trace driver bank
are nearly uniformly distributed over an interval of 4.4ns.
The worst case total load current slew rate on the VCC_25_A supply is estimated from
the above to be ~2.2GA/s.
5.2.2 VCC_OUT1, VCC_OUT2 Supplies
In simulation, the tail currents of trace driver output stages turn on in as little as 10ns.
Should all outputs be configured for maximum swing and enabled simultaneously, the
load current step on each of VCC_OUT1, VCC_OUT2 would be as high as 4.26A (for
AC-coupled applications) in ~14ns, 11ns respectively (including the propagation delay
spread noted above). That large dI/dt can be reduced by appropriate programming of
updates. The VCC_OUT1 and VCC_OUT2 supply current drawn by each trace driver
drops in as little as 1ns upon the assertion of device reset. The greater spread of signal
arrival times in the top bank leads to a significantly smaller magnitude of dI/dt on the
VCC_OUT1 supply than on the VCC_OUT2 supply.
GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
GENDOC-053317 March 2013
www.semtech.com
42 of 47
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