GX3290 Datasheet, PDF (27/47 Pages) Semtech Corporation – 290 x 290 3.5Gb/s Crosspoint Switch

EXT_PG1/EXT_PG1
Input 289 Crosspoint Core Output 289
(290 x 290)
MON1/MON1
/2 /11
Serializer/
Pattern
Generator
Pattern
/2 CMU _{Generator 1}
xtal osc.
27MHz
CDR
/2
Pattern
Checker 1
Neutral
Phase
Deserializer
Variable
Phase
Deserializer
Pattern Checker
Figure 4-2: Simplified Pattern Generator/Checker One Block Diagram
Note 1: There are two pattern checker “Rx” blocks in the GX3290. In the following,
wherever only RX0 is mentioned, the corresponding is also true for RX1.
The CDR integrated in each Rx block can independently lock to data at rates of 270Mb/s,
1.485Gb/s and 2.97Gb/s. Other rates up to 3Gb/s can be analyzed by providing an
external clock signal of 2x, 4x, or 22x the desired bit rate, with a maximum external
clock frequency of 6GHz. Note that retiming is not possible when using an external
clock signal for the Rx block. The external clock must be synchronous with any data to
be checked and the RX0_PRBS_CHK_MODE bits must be set to a value of '01'. The two
pattern checker “Rx” blocks in the GX3290 can each independently check PRBS 2⁷-1,
PRBS 2¹⁵-1, and PRBS 2²³-1 data patterns.
Table 4-6: Rx External Clocks
RX0
EXT_CLK0 (R35)
EXT_CLK0 (T35)
RX1
EXT_CLK1 (AJ15)
EXT_CLK1 (AH15)
The error checking modes are selected by the RX0_PRBS_CHK_MODE bits and the
RX1_PRBS_CHK_MODE bits (addresses 0x804h and 0x810h respectively).
GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
GENDOC-053317 March 2013
www.semtech.com
27 of 47
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