GX3290 Datasheet, PDF (23/47 Pages) Semtech Corporation – 290 x 290 3.5Gb/s Crosspoint Switch

Table 4-3: Serial Data Output (Continued)
ACTIVE_SIGNAL_INVERT[287:0],
DYNAMIC_SIGNAL_INVERT[287:0],
MON0_SIGNAL_INVERT or MON1_SIGNAL_INVERT
0
1
ACTIVE_POWER_DOWN[287:0],
DYNAMIC_POWER_DOWN[287:0], MON0_POWER_DOWN
or MON1_POWER_DOWN
0
1
Status
Not inverted
Inverted
Status
On
Off
4.3 Crosspoint Switch Matrix Operation
The crosspoint switch matrix routes the serial digital input signals
(SDI[0:287]/SDI[0:287], EXT_PG0/EXT_PG0 or EXT_PG1/EXT_PG1) to one or more serial
digital outputs (SDO[0:287]/SDO[0:287], MON0/MON0 or MON1/MON1). The matrix is
configured on a per output basis. Each serial digital output can be configured to accept
a signal from one serial digital input. Multiple serial digital outputs can accept input
from the same serial digital input.
Updates to the switch matrix take place as soon as they are written to the host interface
when controlling the device through the ACTIVE Configuration and Status Registers.
These registers are the ACTIVE[287:0], MON0, and MON1 registers found in Section 2
of the Crosspoint (GX3290 and family) Reference Manual (for CSRs) document.
Before the ACTIVE[287:0], MON0, and MON1 registers at addresses 0x200h through
0x321h can be directly used to update the crosspoint switch matrix, an initialization
procedure is required. One of the UPDATE_EN[7:0] pins needs be toggled from a low
state to a high state, and back to a low state again.
Alternatively, set the SOFTWARE_UPDATE_ENABLE bit in the CONTROL_SETUP
register at address 0xA00h to a value of 1, and then toggle one of the
SOFT_UPDATE_EN[7:0] bits in the SOFT_UPDATE_CONTROL register at address
0xA01h from a value of 0 to a value of 1, and then back to a value of 0.
If the ACTIVE[287:0], MON0, and MON1 registers are not being directly written by the
system controller, this procedure is not required. Reading from the ACTIVE[287:0],
MON0, and MON1 registers will work regardless of whether or not the above
procedure is executed.
Updating the crosspoint switch matrix using the DYNAMIC[287:0] registers (discussed
below) does not require the initialization procedure described above.
The switch matrix can also be updated using double-buffering when controlling the
device through the DYNAMIC Configuration and Status Registers. These registers are
DYNAMIC[287:0] in Section 1 of the Crosspoint (GX3290 and family) Reference
Manual (for CSRs) document.
GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
GENDOC-053317 March 2013
www.semtech.com
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