GX3290 Datasheet, PDF (25/47 Pages) Semtech Corporation – 290 x 290 3.5Gb/s Crosspoint Switch

4.6 Pattern Generator and Pattern Checker
4.6.1 Pattern Generator
Note 1: There are two pattern generator “Tx” blocks in the GX3290. In the following,
wherever only TX0 is mentioned, the corresponding is also true for TX1.
Note 2: When the PRBS Generator is disabled, the generated signal does not completely
terminate. The PRBS polynomial bits must be re-written in order to terminate the signal.
The two pattern generator “Tx” blocks in the GX3290 can each independently generate
PRBS 2⁷-1, PRBS 2¹⁵-1, and PRBS 2²³-1 data patterns, or alternating 1's and 0's. The
built-in clock multiplier PLLs independently synthesize rates of 270Mb/s and 2.97Gb/s
from the required, external 27MHz reference clock (see Section 4.9). Other rates up to
3Gb/s can be generated by providing an external clock signal at 2x, 4x, or 22x the
desired bit rate to TX1, with a maximum external clock frequency of 6GHz.
Table 4-4: Tx External Clocks
TX0
EXT_CLK_DIGITAL (AJ35)
EXT_CLK_DIGITAL (AH35)
TX1
EXT_CLK2 (R15)
EXT_CLK2 (T15)
While this facility exists for both TX0 and TX1, the user is cautioned that the digital core
clock is derived from the TX0 data clock, and therefore interface and update timing will
track the external clock frequency if one is provided to TX0.
The pattern generators are enabled by the TX0_PRBS_GEN_ENABLE and
TX1_PRBS_GEN_ENABLE bits (register address 0x802h, bits [1:0] respectively).
The PRBS generating polynomials used are:
1. PRBS7: x⁷ + x⁶ + 1
2. PRBS15: x¹⁵ + x¹⁴ + 1
3. PRBS23: x²³ + x¹⁸ + 1
The pattern generated is selected via the TX0_PRBS_POLYNOMIAL and
TX1_PRBS_POLYNOMIAL bits (register address 0x800h and 0x801h respectively).
Table 4-5: Generated Patterns
TX0_PRBS_POLYNOMIAL[1:0] (binary)
00
01
10
11
Pattern Generated
PRBS7
PRBS15
PRBS23
Square Wave
GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
GENDOC-053317 March 2013
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