GX3290 Datasheet, PDF (19/47 Pages) Semtech Corporation – 290 x 290 3.5Gb/s Crosspoint Switch

DIGITAL_CL_SEL
EXT_CLK_DIGITAL
EXT_CLK_DIGITAL
REF_CLK_IN
REF_CLK_OUT
XTAL
OSC.
/2
CMU
0
Pattern
TX0
1
Note: The clock used to drive Pattern Generator TX0 is also used to derive
the clock timing for the digital core. Therefore, GSPI/APPI interface timing
and update timing will track the external clock frequency if one is selected
from the EXT_CLK_DIGITAL/EXT_CLK_DIGITAL pins for Pattern Generator TX0.
EXT_CLK0
EXT_CLK0
REF_CLK_IN
REF_CLK_OUT
EXT_CLK1
EXT_CLK1
REF_CLK_IN
REF_CLK_OUT
BIST_RX_5 0x83C b4
/2
XTAL
OSC.
CMU
0
Pattern
RX0
1
BIST_RX_5 0x83C b6
/2
XTAL
OSC.
CMU
0
Pattern
RX1
1
EXT_CLK2
EXT_CLK2
REF_CLK_IN
REF_CLK_OUT
BIST_TX_0 0x823 b0
/2
XTAL
OSC.
CMU
0
Pattern
TX1
1
Figure 3-5: PRBS Generator/Checker Clock Selection
REF_CLK_IN
REF_CLK_OUT
Using a crystal
1MΩ
C1
27MHz
C2
Using a single-ended 27MHz oscillator
REF_CLK_IN
27MHz Oscillator
REF_CLK_OUT
Note: The value of the C1 and C2 load capacitors are
dependent on the chosen crystal.
Figure 3-6: Crystal Oscillator
GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
GENDOC-053317 March 2013
www.semtech.com
19 of 47
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