LC78626E Datasheet, PDF (9/32 Pages) Sanyo Semicon Device – DSP for Compact Disk Players

LC78626E
Description of Pins
Pin
Pin
No.
Name
1 DEFI
2 TAI
3 PDO
4
VV_SS
5 ISET
6
VV_DD
7 FR
8
V_SS
9 TESCLK
10 TESA
11 TESB
12 TESC
13 TESGB
14 TEST5
15 CS
16 TEST1
17 EFMO
18 EFMI
19 TEST2
20 CLV⁺
21 CLV^–
22 V/P
23 HFL
24 TES
25 TOFF
26 TGL
27
JP⁺
28
JP^–
29 PCK
30 FSEQ
31
V_DD
32 ASRES
33 CONT2
I/O
Function
I Defect detection signal (DEF) input. When not used, must be connected to 0 V.
I
Test input. Equipped with internal pull-down resistor. Must be connected to 0V.
O
External VCO control phase comparator output.
P
Internal VCO ground. Must be connected to 0 V.
For the PLL
AI
PDO output current adjustment resistor connection.
P
Internal VCO power supply.
AI
VCO frequency range adjustment
P Digital system ground. Must be connected to 0 V.
I Test clock input. Must be connected to VDD.
I Test operation mode control input. Must be connected to VDD.
I Test operation mode control input. Must be connected to VDD.
I Test operation mode control input. Must be connected to VDD.
I Test operation mode control input. Must be connected to VDD.
I Test input. Equipped with internal pull-down resistor. Must be connected to 0 V.
I Chip select input. Equipped with internal pull-down resistor. When not controlled, must be connected to 0 V.
I Test input. Must be connected to 0 V.
O For slice
EFM signal output.
I level control. EFM signal input.
I Test input. Equipped with internal pull-down resistor. Must be connected to 0 V.
O
Disk motor control output. Can have a 3-state output depending on the command.
O
Rough servo/phase control automatic switching monitor output. If a high level then rough servo mode. If a low level then
O _{phase control mode.}
I Track detect signal input. Schmidt input.
I Tracking error signal input. Schmidt input.
O Tracking off output.
O Tracking gain switch output. Gain is increased with low level.
O
Track jump control output. Can be 3-state output depending on the command.
O
O EFM data playback clock monitor. 4.3218 MHz during phase lock.
Sync signal detect output. A high level when the sync signal detected from the EFM signal matches the internally
O _{generated sync signal.}
P Digital system power supply.
I(I/O)
Reset signal input for initializing only the anti-shock control part (i.e. excluding the DSP part). Resets when this
pin is low level, and release the reset when this pin is high level. Tie this pin to the low level (i.e., connected to 0 V) if
when using software control on the anti-shock part alone through the anti-shock part only reset disable/release
command ($F4) or the anti-shock only reset enable/inrush command ($F5).
Note: This pin is assigned as the least significant bit of the general I/O port however, use as a general I/O
pin is disabled. When the port I/O set command ($DB) is executed, the least significant bit is always “0,” and the
output driver is not turned ON.
General I/O pin 2. This controls the commands from the microcontroller. When not used, either set this as an input
I/O _{port and connect to 0 V, or set this as an output port and leave it open.}
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