LC78626E Datasheet, PDF (19/32 Pages) Sanyo Semicon Device – DSP for Compact Disk Players

LC78626E
The THLD Signal is generated on the LA9230M, 9240M Series side, and causes the tracking error signal to be held
during the JP pulse period.
* The Tracking Brake
The relationship between the TES, HFL, and TOFF signals during the track jump period c is as shown below. The
TOFF signal is generated from the HFL signal with the changing edge of the TES signal. The high of the HFL signal
is for the mirrored area, while the low is for the pitted area. As the beam sweeps from the mirrored surface to the
pitted area, TOFF becomes high, and as the beam sweeps from the pitted area to the mirrored surface, TOFF is made
low in the gain-enhanced state (TGL low), and the brake is applied.
TES (when moving towards the outside)
TES (when moving towards the inside)
HFL
TOFF output
(4) The JP 3-state Output
Code
$B6
$B7
COMMAND
JP 3-state output
JP 2-state output (conventional method)
RES = low
q
Using the JP 3-state command, the track jump can be controlled with a single pin, however, the gain must be
increased on the servo side because the kick gain will decrease by 6 dB.
2-state output
3-state output
High impedance output
(5) The Track Check Mode
Code
$F0
$F8
$FF
COMMAND
Track check IN
Track check OUT
Two byte command reset
RES = low
q
After the track check IN or track check OUT command has been entered, then when a discretionary number between
8 and 254 is entered as binary data, a track count of the specified number - 1 will be performed.
The number of desired track checks = the number of track checks input – 1
Command
Track check
Track check Binary input of the desired
In/Out command number of tracks + 1
Double byte
command reset
Brake command
Rising edge at the Goes low when the track
number of tracks/2
check is complete.
No. 5692-19/32