LC78626E Datasheet, PDF (27/32 Pages) Sanyo Semicon Device – DSP for Compact Disk Players

LC78626E
(2) C1 and C2 Corrections
Data that has been EFM modulated is written to the internal RAM, the jitters are absorbed, and then, the following
processes are performed with uniform timing through the crystal oscillator clock. First, there is error checking and
correction as the C1 block, the C1 flag is determined and written to the C1 flag register. Next, error checking and
corrections are performed as the C2 block, and the C2 flag is determined and written to the internal RAM.
C1 Check
No error
1 error
2 errors
3 or more errors
Correction and Flag Process
Correction not required/flag is reset
Correction performed/flag is reset
Correction is performed and flag is set
Correction is not possible and flag is set
C2 Check
No error
1 error
2 errors
3 or more errors
Correction and Flag Process
Correction not required/flag is reset
Correction performed/flag is reset
See the C1 flag. (Note 1)
See the C1 flag. (Note 2)
Note: 1. If the error position determined by the C2 check matches the C1 flag, then the error correction is performed and the flag is reset. However, when
there are seven or more C1 flags, then there would be the risk of an erroneous correction, and thus no correction is performed and the C1 flags
become C2 flags. When one of the error positions match, but another error position does not match, then no correction can be performed. Moreover,
when there are five or less C1 flags, then the C1 check is thought to be somewhat dubious, and thus the flag is set. When there are six or more, the
error correction is not possible and they are handled together, so the C1 flags become C2 flags as they are. When none or the error positions match,
naturally error correction cannot be performed, and when the number of C1 flags is two or less, then there may be errors even in the data that was
deemed OK by the C1 check, and thus the flag is set. In other cases, the C1 flags are used as C2 flags as they are.
2. When it is determined that error correction is not possible because there are three or more errors, then naturally error correction cannot be
performed and when the number of C1 flags is two or less, even the data that was deemed as OK in the C1 check may contain errors, and thus the
flags are set. In other cases, the C1 flags are used as C2 flags directly.
25 The Anti-shock Function Pin 67: FMT, Pin 48: MR1, Pin 76: WOK, Pin 75: CNTOK, Pin 74: OVF, Pin 46:
C2F, Pin 66: WRQ, Pin 65: SQOUT
The anti-shock function of this IC reads data from the disk at double speed and stores it in the external DRAM. By
replaying that data that was stored when an external shock has caused the data acquisition to be defective, it is
possible to avoid defective playback due to external shocks. The anti-shock mode is set by placing the FMT pin high.
When the data is stored in external DRAM, the 16-bit data is compressed to 5 bits using ADPCM. Depending on the
DRAM capacity (256K x 4 bits or 1M x 4 bits) the time that can be stored will be approximately 2.4 seconds (1M) or
approximately 9.5 seconds (4M). Depending on the type of DRAM, the MR1 might have to be set. (See the table.)
When in the anti-shock mode, the double speed data is written to the external DRAM and then read at normal speed
(1x speed) for playback, and thus the external DRAM will eventually become full. When this happens, this IC stops
writing to the DRAM and places the OVF pin high. The microcontroller monitors the OVF and when the
microcontroller senses that the OVF signal has gone high, it places the WOK pin low and in order to find the point at
which the writing was terminated (called the "L" point below) the system must perform a track jump. The
microcontroller has already determined through its monitoring of the frame number in the subcode Q the location of
the L point. The frame number at the point when the OVF pin becomes high track jumps to the location, and the L
point is sought by placing the WOK pin high that many frames earlier. When this IC finds the L point, the CNTOK
pin is put high, and the DRAM data write process begins again. Furthermore, sometimes the L point cannot be found,
such as when there is an external shock during the L point search. If the CNTOK pin has not become high even if the
L point frame number has been passed (by three or more frames), then it is determined that the L point was not found.
When this happens, a track jump is performed again, and the L point search begins again. When the search is
performed again, the track jump is performed with the WOK pin High. This IC determines whether or not there has
been an external shock through the use of the C2F flag. When the C2F flag becomes high then the OVF pin becomes
high just as if the DRAM was full, and writing to the DRAM is terminated. In this case, the microcontroller should
perform the same process as if the DRAM had become full.
The Setting pins
Pin
FMT
MR1
High
Anti-shock mode: ON
1M bit (256K × 4 bit) DRAM
Low
Anti-shock mode: OFF
4M bit (1M × 4 bit) DRAM
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