LC78626E Datasheet, PDF (26/32 Pages) Sanyo Semicon Device – DSP for Compact Disk Players

LC78626E
22 The Reset Circuit Pin 69: RES
When the power supply is turned on, first set this pin low and then set it to high. The muting is set to –∞dB and the
disk motor is set to stop.
CLV servo relationship
START
STOP
BRAKE
CLV
Muting control
0dB
–∞
Subcode Q address parameter
Address1
Address Free
Track jump mode
Conventional
New
Track count mode
Conventional
New
Digital attenuator
DATA0
DATA 00H to EEH
OSC
ON
OFF
Playback speed
Normal speed
Double speed
Digital filter normal speed
ON
OFF
When the RES pin is low, then the statuses found in the boxes above are set directly.
23 Other Pins Pin 2: TAI, Pin 16: TEST1, Pin 19: TEST2, Pin 38: TEST3, Pin 40: TEST4, Pin 14: TEST5
These are pins for testing the circuits within the IC. While TAI and TEST1 to TEST5 are equipped with internal pull-
down resistors, for safety reasons, they should be connected to 0 V.
24 Explanation of the Block Functions
(1) RAM Address Control
This IC contains 8 bits × 2K words on on-board RAM, and, depending on the address control, the EFM modulation
data jitter absorption capability can have ± 4 frames as the buffer memory capacity. Moreover, normally this buffer
margin is checked, and by precisely controlling the CLV servo circuit PCK-side frequency ratio it is possible to
control the data write address so that it will be centered on the size of the buffer. Also, when the ± 4 frame buffer
capacity is exceeded, the write address can be forced to ± 0, and because the resulting errors cannot be subjected to
flag processing, the mute is applied for a 128 frame period.
Position
–4 or lower
–3
–2
–1
±0
+1
+2
+3
+4 or greater
Frequency Divider Ratio or Process
Forces transition to ± 0
589
589
Forward frequency division
589
588
Standard frequency division
587
587
Backwards frequency division
587
Forces transition to ± 0
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