LC78626E Datasheet, PDF(16/32 Page) Sanyo Semicon Device

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LC78626E Datasheet, PDF (16/32 Pages) Sanyo Semicon Device – DSP for Compact Disk Players

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LC78626E

(5) The Internal Brake Mode

Code

COMMAND

RES = low

$C5

Internal Break ON

$C4

Internal Break OFF

$A3

Internal brake control

$CB

Internal brake continuous mode

$CA

Internal brake continuous mode reset

$CD

Internal brake TON mode

$CC

Internal brake TON mode reset

* The internal brake mode is turned on by inputting the internal brake on command ($C5). When in this mode, when

the brake command ($06) is executed it becomes possible to monitor the state of deceleration of the disk using the

WRQ pin.

* In this mode, the status of deceleration of the disk is determined by counting the density of the EFM signals in a

single frame, and the CLVâ is low if the number of EFM signals is 4 or less. At the same time, the WRQ signal is

put to high as the break complete monitor. The microcontroller issues the STOP command if it senses that the

WRQ signal is high, and thus brings the disk to a complete stop. In the internal break continuous mode the CLVâ =

high brake operation continues even when the break complete monitor WRQ goes high.

When noise in the EFM signal causes the deceleration status to be judged incorrectly, it may be advisable to use the

internal break control command ($A3) to change the EFM signal count from 4 to 8.

* In the TOFF output inhibited mode ($CD), TOFF is low while the internal break is in operation. Its use is

recommended because it is effective in preventing incorrect detection at the mirrored surface of the disk.

EFM signal

$06 command

* When there is a loss of focus during the execution of an internal break command it will be necessary to reissue the

internal brake command after the focus has been reestablished.

* Because there is a risk that the EFM signal will be discerned incorrectly depending on the playback status

(scratched disks, access processes, etc.), use in conjunction with the microcontroller is recommended.

* When the internal brake mode is in effect, then it is possible to monitor the disk deceleration status at the WRQ Pin

by executing the DISC MTR BRAKE command ($06) in this DSP. However, if another command is executed

while this command is in process, then the command will be aborted. When you wish to prevent the function from

being aborted, then, after issuing the DISC MTR BRAKE command ($06), do not issue any other commands until

a high WRQ signal is detected and the DISC MTR STOP command ($07) is issued.

7 The Track Jump Circuit Pin 23: HFL, Pin 24: TES, Pin 25: TOFF, Pin 26: TGL, Pin 27: JP+, Pin 28: JPâ

(1) Types of Track Counters

The following two track count modes have been provided.

Code

$22

$23

COMMAND

The new track count (a combination of TES and HFL).

The conventional track count (direct count of the TES signal).

RES = low

The conventional track counter uses the TES signal itself as the internal track counter clock. In the new track count

method, however, the TES signal is combined with the HFL signal to reduce the amount of noise, producing a more

accurate track count through reducing the number of miscounts due to noise in the rising edge and falling edge of the

TES signal. However, when the HFL signal is absent because of dust, scratches, etc., there is the danger that there

will be no track count pulse, and thus caution is required when using this method.

No. 5692-16/32

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