LC89052TA-E Datasheet, PDF (39/42 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89052TA-E
Table 9.10 Output Register: Input fs Calculation Result and Channel Status Data (0xEC)
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
0
0
FSCAL2
FSCAL1
FSCAL0
0
OUTPCM
OUTERR
0
8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
32
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
40
Bit 39
Bit 38
Bit 37
Bit 36
Bit 35
Bit 34
Bit 33
Bit 32
48
Bit 47
Bit 46
Bit 45
Bit 44
Bit 43
Bit 42
Bit 41
Bit 40
• The error information, non-PCM information, input fs calculation result, and channel status data can be read from this
register. Note that the error information and the non-PCM data information are identical to those at 0xEB.
OUTERR:
OUTPCM:
ERROR output (Outputs the read-time state.)
0: No transmission error in the PLL locked state
1: Either a transmission error occurred or the PLL circuit is in the unlocked state.
____________
AUDIO output (Outputs the read-time state.)
0: Non-PCM signal not detected.
1: Non-PCM signal detected.
• The input data fs calculation results are allocated as follows. The target calculation frequency differs depending on the
FS4XIN setting. The calculation range also differs slightly depending on the XIN clock frequency.
FSCAL2
0
0
0
0
1
1
1
1
Table 9.11 Input fs Calculation Result (Ta = 25°C, VDD = 3.3V, XIN = 11.2896MHz)
FSCAL1
FSCAL0
Target fs
FS4XIN = 0
Calculated range
Target fs
FS4XIN = 1
Calculated range
0
0
Out of range
—
Out of range
—
0
1
32kHz
30.9k to 33.2kHz
64kHz
62.0k to 66.4kHz
1
0
44.1kHz
42.5k to 45.8kHz
88.2kHz
85.5k to 91.0kHz
1
1
48kHz
46.3k to 49.9kHz
96kHz
92.6k to 99.0kHz
0
0
64kHz
62.1k to 66.4kHz
128kHz
124.0k to 132.8kHz
0
1
88.2kHz
85.6k to 91.0kHz
176.4kHz
171.0k to 182.2kHz
1
0
96kHz
92.6k to 99.0kHz
192kHz
185.1k to 198.0kHz
1
1
—
—
—
—
• The first 48 bits of channel status can be read.
• Since the channel status consists of 192 frames, updated data can always be read by reading at the interval 192 times
the period of the input sampling frequency.
• It is also possible to read by using the updated flag of the interrupt source and setting E/INT to interrupt output to
reduce the load of the microcontroller. This flag is output when the first 48 bits of the current data is compared with
the data of the previous block and found that those data are identical.
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