LC89052TA-E Datasheet, PDF (11/42 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89052TA-E
8.3 Clocks
8.3.1 PLL (LPF)
• The LC89052TA-E incorporates a VCO (Voltage Controlled Oscillator) that can synchronize with sampling
frequencies of 30kHz to 195kHz.
• The locking frequency is selected with PLLCK[1:0]. The VCO circuit can be stopped with PLLOPR.
• The range of input data that can be received differs depending on the settings of PLLCK[1:0].
• The (512/2)fs for the PLLCK[1:0] = "11" in the table below is the state where the PLL itself is synchronized with the
512fs clock, but the clock signal output from the CKOUT pin is 1/2 of the PLL locked frequency, which is 256fs.
See the chapter on the of output clock for further information.
• We recommend the 256fs setting with PLLCK[1:0] = "00" for the systems such as portable equipment that need to
restrain the consumption electric power. We also recommend the 512fs setting with PLLCK[1:0] = "10" or the
(512/2)fs with PLLCK[1:0] = "11" for the systems such as AV amplifiers that require improved performance.
PLLCK1
0
0
1
1
Table 8.3 Input Data Reception Ranges and PLL Lock Frequency Settings
PLLCK0
PLL lock frequency
Input data reception range
0
256fs
30k to 195kHz
1
384fs
30k to 108kHz
0
512fs
30k to 108kHz
1
(512/2)fs
30k to 108kHz
• LPF is the PLL loop filter connection pin. Use the correct recommended resistance and capacitance as values listed in
the table below according to the PLLCK[1:0] settings.
LPF
R0
C1
C0
PLLCK1
0
0
1
1
PLLCK0
0
1
0
1
R0
150Ω
150Ω
Figure 8.2 PLL Loop Filter Configuration
C0
0.047µF
0.068µF
C1
0.0068µF
0.0047µF
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