LC89052TA-E Datasheet, PDF (33/42 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89052TA-E
DI7
FSSEL3
DI15
0
Table 9.6 Input Register Function Settings 1: I/O Data Settings (0xE9)
DI6
DI5
DI4
DI3
DI2
DI1
FSSEL2
FSSEL1
FSSEL0
FS4XIN
FLIMIT
GPIDAT
DI14
DI13
DI12
DI11
DI10
DI9
RDTMUT
RDTSTA
RDTSEL
0
OFSEL2
OFSEL1
GPISEL:
GPIDAT:
__________
UGPI pin setting
0: Outputs the microcontroller interface register state. (initial value)
1: Outputs clock switching transitional period signal.
__________
UGPI output setting (valid only when register output mode is set.)
0: Outputs the low level.
1: Outputs the high level. (initial value)
DI0
GPISEL
DI8
OFSEL1
FLIMIT:
Input data reception limit setting
0: Reception is not limited. All data within the PLL locked range can be received.
(initial value)
1: Reception is limited. The input fs calculation result is reflected in the error flag
according to the FSSEL[3:0] setting.
FS4XIN:
Input fs calculation range setting
0: Perform fs calculation for input data in the range of 32k to 96 kHz. (initial value)
1: Perform fs calculation for input data in the range of 64k to 192 kHz.
FSSEL[3:0]:
Input data reception range setting (When FLIMIT = "1" and FS4XIN = "0")
0000: 32k, 44.1k, 48k, 64k, 88.2k, or 96kHz (initial value)
0001: 32kHz only
0010: 44.1kHz only
0011: 48kHz
0100: 88.2kHz only
0101: 96kHz only
0110: 44.1k or 88.2kHz only
0111: 48k or 96kHz only
1000: 32k or 44.1k or 48kHz
1001-1111:Reserved
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