LC89052TA-E Datasheet, PDF (14/42 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89052TA-E
• The tables below show the output clocks generated in the XIN and PLL clock source modes.
Table 8.5 XIN Output Clocks in Clock Source Mode (XISEL2 = "0", PLL unlocked state or forced setting)
PLLCK1
PLLCK0
XISEL1
XISEL0
CKOUT pin
BCK pin
LRCK pin
0
0
0
0
11.2896MHz
2.8224MHz
44.1kHz
0
0
0
1
12.2880MHz
3.0720MHz
48kHz
0
0
1
0
16.9344MHz
4.2336MHz
66.15kHz
0
1
0
0
11.2896MHz
1.8816MHz
29.4kHz
0
1
0
1
12.2880MHz
2.0480MHz
32kHz
0
1
1
0
16.9344MHz
2.8224MHz
44.1kHz
1
0
0
0
11.2896MHz
2.8224MHz
44.1kHz
1
0
0
1
12.2880MHz
3.0720MHz
48kHz
1
0
1
0
16.9344MHz
4.2336MHz
66.15kHz
1
1
0
0
11.2896MHz
2.8224MHz
44.1kHz
1
1
0
1
12.2880MHz
3.0720MHz
48kHz
1
1
1
0
16.9344MHz
4.2336MHz
66.15kHz
Table 8.6 XIN Output Clocks in Clock Source Mode (XISEL2 = "1", PLL unlocked state or forced setting)
PLLCK1
PLLCK0
XISEL1
XISEL0
CKOUT pin
BCK pin
LRCK pin
0
0
0
0
22.5792MHz
5.6448MHz
88.2kHz
0
0
0
1
24.5760MHz
6.1440MHz
96kHz
0
0
1
0
33.8688MHz
8.4672MHz
132.3kHz
0
1
0
0
22.5792MHz
3.7632MHz
58.8kHz
0
1
0
1
24.5760MHz
4.0960MHz
64kHz
0
1
1
0
33.8688MHz
5.6448MHz
88.2kHz
1
0
0
0
22.5792MHz
5.6448MHz
88.2kHz
1
0
0
1
24.5760MHz
6.1440MHz
96kHz
1
0
1
0
33.8688MHz
8.4672MHz
132.3kHz
1
1
0
0
22.5792MHz
5.6448MHz
88.2kHz
1
1
0
1
24.5760MHz
6.1440MHz
96kHz
1
1
1
0
33.8688MHz
8.4672MHz
132.3kHz
PLLCK1
0
0
1
1
Table 8.7 PLL Output Clocks in Clock Source Mode (PLL locked state)
PLLCK0
CKOUT pin
BCK pin
0
256fs
64fs
1
384fs
64fs
0
512fs
64fs
1
256fs
64fs
LRCK pin
fs
fs
fs
fs
• The CKOUT output clock frequency can be set to 1/2 of its normal value with MCKHFO, regardless of the PLL
locked/unlocked state. Clock switching with this setting can be done without unlocking the PLL but clock continuity
is not maintained.
• If the audio output format is set to bi-phase data output, the BCK output clock frequency is doubled to 128fs when the
PLL circuit is locked. However, when unlocked, a BCK signal shown in the above tables is output. Note that the
clock continuity is not maintained when this output format is set.
No.7457-14/42