LC89052TA-E Datasheet, PDF (29/42 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

9.5 Input/Output Timing
LC89052TA-E
CE
CL
DI
B0 B1 B2 B3 A0 A1 A2 A3
DI0
DI1 DI2 DI3 DI4 DI5 ^{. . . .} DI15
DO
Hi-Z
Figure 9.1 Input Timing Chart (Normal low clock)
CE
CL
DI
B0 B1 B2 B3 A0 A1 A2
A3
DI0 DI1 DI2 DI3 DI4 DI5 ^{. . . .} DI15
DO
Hi-Z
Figure 9.2 Input Timing Chart (Normal high clock)
CE
CL
DI
B0 B1 B2 B3 A0 A1 A2 A3
DO
Hi-Z
DO0 DO1 DO2 DO3 DO4 ^{. . . . . . .} DOn
Figure 9.3 Output Timing Chart (Normal low clock)
CE
CL
DI
B0 B1 B2 B3 A0 A1 A2 A3
DO
Hi-Z
DO0 DO1 DO2 DO3 DO4 ^{. . . . . . . . . . . .} DOn
Figure 9.4 Output Timing Chart (Normal high clock. It is necessary to read DO0 with a port.)
• In the output timing shown in figure 9.4, data is allocated so that there are no problems even if the output register
DO0 is not read. See the read register table for details.
No.7457-29/42