LC89052TA-E Datasheet, PDF (34/42 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89052TA-E
FSSEL[3:0]:
Input data reception range setting (When FLIMIT = "1" and FS4XIN = "1")
0000: 64k, 88.2k, 96k 128k, 176.4k, or 192kHz (initial value)
0001: 64kHz only
0010: 88.2kHz only
0011: 96kHz only
0100: 176.4kHz only
0101: 192kHz only
0110: 88.2k or 176.4kHz only
0111: 96k or 192kHz only
1000: 64k or 88.2k or 96kHz only
1001-1111: Reserved
OFSEL[2:0]:
Serial audio data output format setting
000: 24-bit MSB first left-justified data output (initial value)
001: 24-bit I²S data output
010: 24-bit MSB first right-justified data output
011: 20-bit MSB first right-justified data output
100: 16-bit MSB first right-justified data output
101-100: Reserved
101: Bi-phase data output
110: 28-bit I²S data output (NRZ data output)
111: 28-bit LSB first left-justified data output (NRZ data output)
RDTSEL:
PLL unlocked state DATAO output setting
0: Output the SDIN data in the PLL unlocked state. (initial value)
1: Mute the output in the PLL unlocked state.
RDTSTA:
DATAO output setting
0: Follow the RDTSEL setting. (initial value)
1: Output the SDIN data regardless of the PLL state.
RDTMUT:
DATAO mute setting
0: Output the data selected by RDTSEL. (initial value)
1: Mute the output.
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