LC89052TA-E Datasheet, PDF (21/42 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89052TA-E
8.5 Error Output Processing (ERROR)
8.5.1 Lock error and data error output
• The ERROR pin outputs high level when a PLL lock error happens or an error occurs in the transmitted data.
8.5.2 PLL lock error
• The PLL circuit will unlock the input data which does not conform to the bi-phase modulation rules or can not detect
the preamble B, M, or W.
• ERROR turns to H when a PLL lock error occurs. When data modulation returns to the normal state, it remains high
for 15m to 50ms, before going to the to low level.
• The output of ERROR is synchronized with LRCK.
8.5.3 Input data transmission error
• An odd number of input parity errors are detected from the parity bits in the input data.
• When input parity errors occur 9 times or more in a row, ERROR turns to high level. After the high level is held for
15m to 50ms following the detection of the PLL lock state, the ERROR returns to low level.
• When 8 or fewer input parity errors occur consecutively, an error is output only for intervals between sub-frames
where the errors occurred when non-PCM data is recognized by data delimiter bit 1 in the channel status. In this case,
the parity error flag is not output when PCM data is recognized.
8.5.4 Other errors
• Even when ERROR has turned to low, the LC89052TA-E always acquires bits 24 to 27 (sampling frequency) of the
channel status and compares the current data with the data of the previous block. If any differences are found,
ERROR is immediately set to high and processes similar to those for the PLL lock error are carried out.
• Similarly, even when the mode that reflects fs calculation results in an error flag is set with FLIMIT, the fs calculation
results are always compared. Here as well, if a disparity occurs in the data, ERROR is immediately turned to high,
and the processing similar to that for the PLL lock error is carried out.
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