LC87F06J2A Datasheet, PDF (3/32 Pages) Sanyo Semicon Device – CMOS IC FROM 192K byte, RAM 8192 byte on-chip 8-bit 1-chip Microcontroller

LC87F06J2A
Continued from preceding page.
• SIO2: 8 bit synchronous serial interface
1) LSB first mode
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 32 bytes)
• SIO 7: 8 bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
• SIO 8: 8 bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
„UART: 2 channels
1) Full duplex
2) 7/8/9 bit data bits selectable
3) 1 stop bit (2 bits in continuous transmission mode)
4) Built-in baudrate generator (with baudrates of 16/3 to 8192/3 tCYC)
„AD Converter
• 8 bits × 16 channels
„PWM
• Multifrequency 12-bit PWM × 4 channels
„Remote Control Receiver Circuit (sharing pins with P73, INT3, T0IN and TOHCP)
1) Noise filtering function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
2) The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read
with an instruction, the signal level at that pin is read regardless of the availability of the noise filtering function.
„Small Signal Detect Function
1) Small Signal Detect Function is available in the following two terminals.
P20/INT4/T1IN/T0LCP/T0HCP/INT6/T0LCP1/SSGI0
P24/INT5/T1IN/T0LCP/T0HCP/INT7/T0HCP1/SSGI1
2) Capable of detecting a pulse with certain level of amplitude.
3) Input bias circuit available.
„H-Counter
1) H-counter can choose one of the following signals as count-clock.
HCTR signal of P22/INT4/T1IN/T0LCP/T0HCP/HCTR terminal
CSYNC signal of PB6/CVD/CSYNC terminal
Composite sync signal detected from CVD (composite Video) signal by built-in sync-separator inputted form
PB6/CVD/CSYNC terminal
2) Counter 7bit (up) + 1bit (over-flow flag)
„Field (first/second) Detect Function
1) Distinguishes a field with one of the following signals.
CSYNC signal of PB6/CVD/CSYNC terminal
Composite sync signal detected from CVD (composite Video) signal by built-in sync-separator inputted form
PB6/CVD/CSYNC terminal
2) Outputs Field-Detect signal from PB0/DS1FLD terminal
„Watchdog Timer
1) External RC watchdog timer
2) Interrupt and reset signals selectable
No.A0432-3/32